Issues with Jetson Nano Production and Jetson-io (and jetpack 4.6 rev1)

Hi,

I’ve been using the Jetson Nano Devkits (with Jetpack 4.6) for some time and I’ve brought up some production Nanos for prototype testing and I’m finding that the jetson-io.py script won’t show anything but the CSI header config options. Will I have to manually create the dtbs myself for this if jetson-io.py doesn’t support this?

Yes, you need implement corresponding device tree and driver for your device.

To be clear, I’m not talking about some custom device of any kind, I just want to enable SPI and have it show up and functional in /dev/spidev0.0. I’ve poked around on the forums a bit, but best practice to do this seems to change fairly often. What’s the latest method?

For SPI you just need to enable the SPI pin configure by jetson-io and reboot and have below command to enable the /dev/spidevX.X

sudo modprobe spidev.ko

You have to enter spidev not spidev.koand yes and I’m aware of this but this only makes spidevX.X available to userspace, but it doesn’t actually relate to the hardware. And as my first post has said, jetson-io doesn’t see the 40pin header at all, much less the SPI options. I’ve decompiled the dtb and there seem to be symbols that relate to a 40hdr so I’m not sure what jetson-io.py is doing. I’ve also tried to change the dtb by extracting the current tree to a dts and adding the pins, but now jetson-io doesn’t work at all. I’m not sure what its looking for.

Also, if I dump tegra_gpio it still shows the SPI pins as 0x1F.

In any case, some clarity on how to make the SPI available from userspace and functional would be appreciated.

1 Like

Below is jetson-io add for the 40-pin, you can check the pin 19,21,23,24,26 was configure as SPI function.

	pinmux@700008d4 {
		compatible = "nvidia,tegra210-pinmux";
		reg = <0x0 0x700008d4 0x0 0x2a5 0x0 0x70003000 0x0 0x294>;
		#gpio-range-cells = <0x3>;
		status = "okay";
		pinctrl-names = "default";
		pinctrl-0 = <0x136>;
		pinctrl-1 = <0x3e>;
		pinctrl-2 = <0x3f>;
		linux,phandle = <0x40>;
		phandle = <0x40>;

		header-40pin-pinmux {
			phandle = <0x136>;
			linux,phandle = <0x136>;

			pin37 {
				nvidia,enable-input = <0x1>;
				nvidia,tristate = <0x0>;
				nvidia,pull = <0x1>;
				nvidia,pins = "spi2_mosi_pb4";
				nvidia,function = "spi2";
			};

			pin28 {
				nvidia,io-high-voltage = <0x1>;
				nvidia,enable-input = <0x1>;
				nvidia,tristate = <0x0>;
				nvidia,pull = <0x0>;
				nvidia,pins = "gen1_i2c_scl_pj1";
				nvidia,function = "i2c1";
			};

			pin27 {
				nvidia,io-high-voltage = <0x1>;
				nvidia,enable-input = <0x1>;
				nvidia,tristate = <0x0>;
				nvidia,pull = <0x0>;
				nvidia,pins = "gen1_i2c_sda_pj0";
				nvidia,function = "i2c1";
			};

			pin26 {
				nvidia,enable-input = <0x1>;
				nvidia,tristate = <0x0>;
				nvidia,pull = <0x2>;
				nvidia,pins = "spi1_cs1_pc4";
				nvidia,function = "spi1";
			};

			pin24 {
				nvidia,enable-input = <0x1>;
				nvidia,tristate = <0x0>;
				nvidia,pull = <0x2>;
				nvidia,pins = "spi1_cs0_pc3";
				nvidia,function = "spi1";
			};

			pin23 {
				nvidia,enable-input = <0x1>;
				nvidia,tristate = <0x0>;
				nvidia,pull = <0x1>;
				nvidia,pins = "spi1_sck_pc2";
				nvidia,function = "spi1";
			};

			pin22 {
				nvidia,enable-input = <0x1>;
				nvidia,tristate = <0x0>;
				nvidia,pull = <0x1>;
				nvidia,pins = "spi2_miso_pb5";
				nvidia,function = "spi2";
			};

			pin21 {
				nvidia,enable-input = <0x1>;
				nvidia,tristate = <0x0>;
				nvidia,pull = <0x1>;
				nvidia,pins = "spi1_miso_pc1";
				nvidia,function = "spi1";
			};

			pin19 {
				nvidia,enable-input = <0x1>;
				nvidia,tristate = <0x0>;
				nvidia,pull = <0x1>;
				nvidia,pins = "spi1_mosi_pc0";
				nvidia,function = "spi1";
			};

			pin18 {
				nvidia,enable-input = <0x1>;
				nvidia,tristate = <0x0>;
				nvidia,pull = <0x2>;
				nvidia,pins = "spi2_cs0_pb7";
				nvidia,function = "spi2";
			};

			pin16 {
				nvidia,enable-input = <0x1>;
				nvidia,tristate = <0x0>;
				nvidia,pull = <0x2>;
				nvidia,pins = "spi2_cs1_pdd0";
				nvidia,function = "spi2";
			};

			pin13 {
				nvidia,enable-input = <0x1>;
				nvidia,tristate = <0x0>;
				nvidia,pull = <0x1>;
				nvidia,pins = "spi2_sck_pb6";
				nvidia,function = "spi2";
			};

			pin10 {
				nvidia,enable-input = <0x1>;
				nvidia,tristate = <0x1>;
				nvidia,pull = <0x2>;
				nvidia,pins = "uart2_rx_pg1";
				nvidia,function = "uartb";
			};

			pin8 {
				nvidia,enable-input = <0x0>;
				nvidia,tristate = <0x0>;
				nvidia,pull = <0x0>;
				nvidia,pins = "uart2_tx_pg0";
				nvidia,function = "uartb";
			};

			pin5 {
				nvidia,io-high-voltage = <0x1>;
				nvidia,enable-input = <0x1>;
				nvidia,tristate = <0x0>;
				nvidia,pull = <0x0>;
				nvidia,pins = "gen2_i2c_scl_pj2";
				nvidia,function = "i2c2";
			};

			pin3 {
				nvidia,io-high-voltage = <0x1>;
				nvidia,enable-input = <0x1>;
				nvidia,tristate = <0x0>;
				nvidia,pull = <0x0>;
				nvidia,pins = "gen2_i2c_sda_pj3";
				nvidia,function = "i2c2";
			};
		};

For your case please apply below patch and add below to your device tree to check if the problem for 0x1F

   gpio_default: default{
   gpio-hog;
   function;
   gpios = <TEGRA_GPIO(C, 0) 0 TEGRA_GPIO(C, 1) 0 TEGRA_GPIO(C, 2) 0 TEGRA_GPIO(C, 3) TEGRA_GPIO(C,4) 0>;

I modified the dtc as per the snippet, confirmed the modification via dtc once the device was flashed. Jetson-io still does not see the header, or the SPI functions.

Can an image file that has a working SPI interface for a Jetson Nano Production eMMC board be provided?

That patch won’t fixed the jetson-io problem. But fixed the GPIO pin configure. Did you apply the kernel patch also?

I haven’t had a chance to cross compile the new kernel and load it yet as I’ve been busy attending to other things, although my understanding is that it was just changing the GPIO registers, but I could fix that with busybox devmem . Also, as I tried to take another look at the dtc I ran into another error that would lock up the nano
[ 29.019307] nvgpu: 57000000.gpu nvgpu_set_error_notifier_locked:137 [ERR] error notifier set to 8 for ch 507
As the nano locked up, I was unable to pull the dmesg/kmsg. I can make it enter recovery mode and reflash it, however.

Is there a timeline on the jetson-io fix? Applying kernel patches and modifying the dts manually seems like a lot of fiddling just to get something as simple as an SPI interface up. Is there an image of a working jetson production eMMC w/ SPI available?

Is your Nano emmc version?
Other’s version without problem to configure by jetson-io.

Yes, as i’ve said before, this is the production eMMC version of the nano. If jetson-io doesn’t work with it, when will this be fixed?

And again, is there an image with functional SPI available for this product?

And yes, I know that jetson-io works for the dev nanos, because that’s what I’ve been using until now and the same code works fine with SPI. That’s how I know the problem is the production nanos.

To be more clear, the product is p3448-0002, as far as I can tell.

Any update @ShaneCCC to the jetson-io situation for the eMMC production Nano Modules? I should have time tomorrow to try recompiling the kernel, but I’d rather just have the jetson-io tools work.

Sorry, I don’t have device on hand to check this week. Will check it next week.

Any update to share @ShaneCCC ?

Apply below patch and replace the tegra210-p3448-0002-p3449-0000-b00.dtb at …/Linux_for_Tegra/kernel/dtb/ and reflash the device by below command.

sudo ./flash jetson-nano-devkit-emmc mmcblk0p1

diff --git a/kernel-dts/porg-platforms/tegra210-porg-gpio-p3448-0002-b00.dtsi b/kernel-dts/porg-platforms/tegra210-porg-gpio-p3448-0002-b00.dtsi
index ac8bda8..a6f455b 100644
--- a/kernel-dts/porg-platforms/tegra210-porg-gpio-p3448-0002-b00.dtsi
+++ b/kernel-dts/porg-platforms/tegra210-porg-gpio-p3448-0002-b00.dtsi
@@ -26,35 +26,13 @@

                gpio_default: default {
                        gpio-input = <
-                               TEGRA_GPIO(BB, 0)
-                               TEGRA_GPIO(B, 4)
-                               TEGRA_GPIO(B, 5)
-                               TEGRA_GPIO(B, 6)
-                               TEGRA_GPIO(B, 7)
-                               TEGRA_GPIO(DD, 0)
-                               TEGRA_GPIO(E, 6)
-                               TEGRA_GPIO(S, 5)
                                TEGRA_GPIO(A, 5)
                                TEGRA_GPIO(X, 4)
                                TEGRA_GPIO(X, 5)
                                TEGRA_GPIO(X, 6)
                                TEGRA_GPIO(Y, 1)
-                               TEGRA_GPIO(Y, 2)
-                               TEGRA_GPIO(V, 0)
                                TEGRA_GPIO(V, 1)
-                               TEGRA_GPIO(Z, 0)
                                TEGRA_GPIO(Z, 2)
-                               TEGRA_GPIO(J, 5)
-                               TEGRA_GPIO(J, 6)
-                               TEGRA_GPIO(J, 4)
-                               TEGRA_GPIO(J, 7)
-                               TEGRA_GPIO(G, 2)
-                               TEGRA_GPIO(G, 3)
-                               TEGRA_GPIO(C, 0)
-                               TEGRA_GPIO(C, 1)
-                               TEGRA_GPIO(C, 2)
-                               TEGRA_GPIO(C, 3)
-                               TEGRA_GPIO(C, 4)
                                TEGRA_GPIO(H, 2)
                                TEGRA_GPIO(H, 5)
                                TEGRA_GPIO(H, 6)