Jetson AGX GPIO control of PCIe power

Hello,

I am trying to control the PCIe 12V output from the AGX Xavier developer kit. I found a diagram in the setup guide that indicates GPIO 05 is used to control the voltage. I need to turn it on and off so I cannot just setup a new pinmux file and flash the board.

In the pinmux configuration xls GPIO05 is GPIO3_PA.01 It is in the audio_hv section but it does have the description GPIO_VDD_12V_ENABLE on CVB so I think this is the correct pin.

I executed the command $ sudo grep tegra-gpio /sys/kernel/debug/gpio
And my GPIO base address is 288

I looked at tegra186-gpio.h and PORT_A is 0

Based on the Linux GPIO number = (base + (8 * port) + pin) I think my GPIO number should be
288 + (8 * 0) + 1 = 289

In trying to understand this better I found this Python library that can drive GPIO outputs GitHub - NVIDIA/jetson-gpio: A Python library that enables the use of Jetson's GPIOs It does not have my GPIO05 in its configuration. I think this is because this GPIO is not located on the 40 pin connector. I did find it uses CAN1_DIN which in pixmux is GPIO3_PAA.01. AA is not a listed port in tegra186-gpio.h. The python program outputs the Linux GPIO number 289 when you read the input for CAN1_DIN.

I don’t understand why my GPIO05 → GPIO3_PA.01 is not 289 and I don’t know where they got the Linux GIPO number for GPI03_PAA.01

Can anyone help?

hello justin,

that’s incorrect header file through the index is zero for port-A also,
please refer to tegra194-gpio.h for Xavier series GPIO header file.
for example,

48  /* GPIOs implemented by AON GPIO controller */
49  #define TEGRA194_AON_GPIO_PORT_AA 0
...

55  #define TEGRA194_AON_GPIO(port, offset) \
56  	((TEGRA194_AON_GPIO_PORT_##port * 8) + offset)

so, please check the gpio number of GPIO3_PAA.01. it’s 248 + (0 * 8) + 1 = 249

Thank you , that is helpful.

I think I am using the correct Linux gpio number of 289 for the PCIe power on the AGX Xavier developer board.

I am getting the error OSError: [Errno16] Device or resource busy when I try to set it high or low. Do I need to do something to ask the PCIe driver to let me control the power?

hello justin,

this failure usually reported by the pin is occupied by other drivers.
please review your pin configurations, thanks

I am trying to control the 12V rails on the PCIe x16 connector J6 on a AGX Xavier Nvidia carrier board.

I am looking at the AGX Xavier Developer Kit Carrier Board Specifications v 2.1. In figure 2-1 PCIe x16 Connector Connections it shows GPIO05 driving the enable pin for a DC-DC 12V chip attached to J6.

I am looking at the AGX Pinmux configuration xls revision 1.06. It lists GIPI05 in the section AUDIO_HV as GPIO3_PA.01. In the column Jetson Dev Kit Usage is has “GPIO_VDD_12V_ENABLE ON CVB”

I calculate the Linux GPIO number as 288 + (8 * 0) + 1 = 289

I am getting the error OSError: [Errno16] Device or resource busy when I try to set it high or low.

What should I do in order to control the 12V rails on the PCIe connector? I have reviewed the pin configurations and I don’t see what I am doing incorrectly.

hello justin,

please check below for the default definition of this pin, you should use the defined DT property to control the pin,
for example,
$L4T_Sources/r32.5/Linux_for_Tegra/source/public/hardware/nvidia/platform/t19x/galen/kernel-dts/common/tegra194-p2888-0000-a00.dtsi

                pcie-reg-enable {
                        gpio-hog;
                        gpios = <TEGRA194_MAIN_GPIO(Z, 2) GPIO_ACTIVE_HIGH
                                 TEGRA194_MAIN_GPIO(A, 1) GPIO_ACTIVE_LOW>;
                        label = "pcie-3v3-reg", "pcie-12v-reg";
                        output-high;
                        status = "okay";
                };