Hello NVIDIA community and Jetson Nano pros!
We successfully designed a custom carrier board for the Jetson Nano module and everything is working fine (USB 2.0, Ethernet, HDMI…).
The problem:
We started the flashing process by powering on the board, while connecting the “FORCE_RECOVERY*” pin of the SoM to GND, and removing it when the the Jetson Nano entered recovery mode. After that, we connected the board to the host machine running Ubuntu 18.04. After running the command “lsusb”, the board was not on the list.
Troubleshooting step 1:
The Jetson Nano board we designed was connected to a host machine running windows 10, and upon the connection of the board, a USB device was detected but not recognized.
Troubleshooting step 2:
This is our design of the micro-USB port (Which is using the exact same components as in the DevKit).
By probing the drain of the MOSFET (Which connects to GPIO0), and comparing it to that of the DevKit, those are the results:
1- On the DevKit: When the USB cable is plugged, GPIO0 transitions from 1.8V to 0V immediately. When the USB cable is removed, GPIO0 transitions from 0V to 1.8V in about 180ms.
2- On our board: When the USB cable is plugged, GPIO0 transitions from 1.8V to 0V immediately. When the USB cable is removed, the transition starts after about 8 seconds, and hits 1.8V after an extra 3 seconds.
I think you may need to add discharge circuit design as below saying in DG.
Power Rail Discharge
To satisfy the power down sequencing requirement and prevent unwanted back drive from the carrier board to the module, the following must be true:
The carrier board 3.3V power supply that powers any module I/O must be off within 1.5 ms of SYS_RESET* assertion.
The 1.8V power supply that powers any module I/O must be off within 4 ms.
The power rails should be fully discharged before attempting to power back up.
Hello and thank you for your reply, the problem seems to be related with D+ and D- being permuted in the design. We fixed that by switching them from the micro-USB cable.
Now everything works fine, the Jetson Carrier was detected by the host, and the OS Image flashing was successful.
Do you think the behavior I described, regarding the delay in GPIO-0, should be of major concern? P.S. I am aware of the power rail discharge and I have implemented the same circuitry for power sequencing as in the original DevKit design files.
You mean the GPIO0 behavior is same as before even after you swap D+ and D-? That is stange if your GPIO0 design is same to reference. Did you probe the voltage level on the 1Mohm or 4.7uF cap? Is it same delay? You may need to compare your design to reference carefully.
