Jetson Thor SPI2对应哪个设备树节点？

BossOfNvidia · December 3, 2025, 7:24am

我需要SPI2进行通信，我在设备树文件tegra264-p3834-0000.dtsi中找到了spi的几个节点，但我不确定SPI2对应哪个节点，是spi@810c440000这个节点么？另外spi@c6c0000这个节点的偏移地址很奇怪，我不确定是不是地址写错了。
设备书节点

		spi@810c590000 {
			status = "okay";
			spi@0 {
				/* chip select 0 */
				compatible = "tegra-spidev";
				reg = <0x0>;
				spi-max-frequency = <50000000>;
			};
		};

		spi@c6c0000 {
			status = "okay";
			spi@0 {
				/* chip select 0 */
				compatible = "tegra-spidev";
				reg = <0x0>;
				spi-max-frequency = <50000000>;
			};
		};

		spi@810c440000 {
			status = "okay";
			spi@0 {
				/* chip select 0 */
				compatible = "tegra-spidev";
				reg = <0x0>;
				spi-max-frequency = <50000000>;
			};
		};

		spi@810c450000 {
			status = "okay";
			spi@0 {
				/* chip select 0 */
				compatible = "tegra-spidev";
				reg = <0x0>;
				spi-max-frequency = <50000000>;
			};
		};

whitesscott · December 3, 2025, 7:58am

grep -iA10 spi2 thor_devkit-pinmux.dtsi

                        qspi2_sck {
                                nvidia,pins = "qspi2_sck";
                                nvidia,function = "qspi2_sck";
                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
                                nvidia,drv-type = <TEGRA_PIN_2X_DRIVER>;
                                nvidia,e-io-od = <TEGRA_PIN_DISABLE>;
                                nvidia,e-lpbk = <TEGRA_PIN_ENABLE>;
                        };

                        qspi2_cs0 {
                                nvidia,pins = "qspi2_cs0";
                                nvidia,function = "qspi2_cs0";
                                nvidia,pull = <TEGRA_PIN_PULL_UP>;
                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
                                nvidia,drv-type = <TEGRA_PIN_2X_DRIVER>;
                                nvidia,e-io-od = <TEGRA_PIN_DISABLE>;
                                nvidia,e-lpbk = <TEGRA_PIN_DISABLE>;
                        };

                        qspi2_d0 {
                                nvidia,pins = "qspi2_d0";
                                nvidia,function = "qspi2_io0";
                                nvidia,pull = <TEGRA_PIN_PULL_UP>;
                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
                                nvidia,drv-type = <TEGRA_PIN_2X_DRIVER>;
                                nvidia,e-io-od = <TEGRA_PIN_DISABLE>;
                                nvidia,e-lpbk = <TEGRA_PIN_DISABLE>;
                        };

                        qspi2_d1 {
                                nvidia,pins = "qspi2_d1";
                                nvidia,function = "qspi2_io1";
                                nvidia,pull = <TEGRA_PIN_PULL_UP>;
                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
                                nvidia,drv-type = <TEGRA_PIN_2X_DRIVER>;
                                nvidia,e-io-od = <TEGRA_PIN_DISABLE>;
                                nvidia,e-lpbk = <TEGRA_PIN_DISABLE>;
                        };

--

        pinmux_unused_lowpower: unused_lowpower {
                        spi2_sck_pcc7 {
                                nvidia,pins = "spi2_sck_pcc7";
                                nvidia,function = "rsvd1";
                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
                                nvidia,drv-type = <TEGRA_PIN_1X_DRIVER>;
                                nvidia,e-io-od = <TEGRA_PIN_DISABLE>;
                                nvidia,e-lpbk = <TEGRA_PIN_DISABLE>;
                        };

                        spi2_miso_pdd0 {
                                nvidia,pins = "spi2_miso_pdd0";
                                nvidia,function = "rsvd1";
                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
                                nvidia,drv-type = <TEGRA_PIN_1X_DRIVER>;
                                nvidia,e-io-od = <TEGRA_PIN_DISABLE>;
                                nvidia,e-lpbk = <TEGRA_PIN_DISABLE>;
                        };

                        spi2_mosi_pdd1 {
                                nvidia,pins = "spi2_mosi_pdd1";
                                nvidia,function = "rsvd1";
                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
                                nvidia,drv-type = <TEGRA_PIN_1X_DRIVER>;
                                nvidia,e-io-od = <TEGRA_PIN_DISABLE>;
                                nvidia,e-lpbk = <TEGRA_PIN_DISABLE>;
                        };

                        spi2_cs0_n_pdd2 {
                                nvidia,pins = "spi2_cs0_n_pdd2";
                                nvidia,function = "rsvd1";
                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
                                nvidia,drv-type = <TEGRA_PIN_1X_DRIVER>;
                                nvidia,e-io-od = <TEGRA_PIN_DISABLE>;
                                nvidia,e-lpbk = <TEGRA_PIN_DISABLE>;
                        };
                };

KevinFFF · December 3, 2025, 9:46am

Hi BossOfNvidia,

Are you using the devkit or custom board for Thor?

You can refer to https://elinux.org/Jetson/L4T/peripheral/#Mapping for the SPI mapping on Thor.

BossOfNvidia · December 3, 2025, 12:26pm

Hi, KevinFFF, the link is on orin, but my board is thor, reg addr may be diffrent.

BossOfNvidia · December 3, 2025, 12:29pm

Hi, whitesscott, i need confirm dts of kernel, instead of BCT.

KevinFFF · December 4, 2025, 7:06am

There’s the section for Thor.

BossOfNvidia · December 4, 2025, 1:26pm

I try it and used spidev_test to test SPI in a loop, but there was no waveform on all spi pins.

-- a/Linux_for_Tegra/bootloader/tegra264-mb1-bct-pinmux-p3834-xxxx-p4071-0000.dtsi
+++ b/Linux_for_Tegra/bootloader/tegra264-mb1-bct-pinmux-p3834-xxxx-p4071-0000.dtsi
@@ -12,7 +12,7 @@
  * 2. Redistributions in binary form must reproduce the above copyright notice,
  * this list of conditions and the following disclaimer in the documentation
  * and/or other materials provided with the distribution.
- * 
+ *
  * 3. Neither the name of the copyright holder nor the names of its
  * contributors may be used to endorse or promote products derived from
  * this software without specific prior written permission.
@@ -1187,10 +1187,10 @@ pinmux@ac281000 {
 
                        spi2_sck_pcc7 {
                                nvidia,pins = "spi2_sck_pcc7";
-                               nvidia,function = "rsvd1";
+                               nvidia,function = "spi2_sck";
                                nvidia,pull = <TEGRA_PIN_PULL_UP>;
-                               nvidia,tristate = <TEGRA_PIN_ENABLE>;
-                               nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                               nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                               nvidia,enable-input = <TEGRA_PIN_DISABLE>;
                                nvidia,drv-type = <TEGRA_PIN_1X_DRIVER>;
                                nvidia,e-io-od = <TEGRA_PIN_DISABLE>;
                                nvidia,e-lpbk = <TEGRA_PIN_DISABLE>;
@@ -1198,7 +1198,7 @@ pinmux@ac281000 {
 
                        spi2_miso_pdd0 {
                                nvidia,pins = "spi2_miso_pdd0";
-                               nvidia,function = "rsvd1";
+                               nvidia,function = "spi2_din";
                                nvidia,pull = <TEGRA_PIN_PULL_UP>;
                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
@@ -1209,10 +1209,10 @@ pinmux@ac281000 {
 
                        spi2_mosi_pdd1 {
                                nvidia,pins = "spi2_mosi_pdd1";
-                               nvidia,function = "rsvd1";
+                               nvidia,function = "spi2_dout";
                                nvidia,pull = <TEGRA_PIN_PULL_UP>;
-                               nvidia,tristate = <TEGRA_PIN_ENABLE>;
-                               nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                               nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                               nvidia,enable-input = <TEGRA_PIN_DISABLE>;
                                nvidia,drv-type = <TEGRA_PIN_1X_DRIVER>;
                                nvidia,e-io-od = <TEGRA_PIN_DISABLE>;
                                nvidia,e-lpbk = <TEGRA_PIN_DISABLE>;
@@ -1220,10 +1220,10 @@ pinmux@ac281000 {
 
                        spi2_cs0_n_pdd2 {
                                nvidia,pins = "spi2_cs0_n_pdd2";
-                               nvidia,function = "rsvd1";
+                               nvidia,function = "spi2_cs0";
                                nvidia,pull = <TEGRA_PIN_PULL_UP>;
-                               nvidia,tristate = <TEGRA_PIN_ENABLE>;
-                               nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                               nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                               nvidia,enable-input = <TEGRA_PIN_DISABLE>;
                                nvidia,drv-type = <TEGRA_PIN_1X_DRIVER>;
                                nvidia,e-io-od = <TEGRA_PIN_DISABLE>;
                                nvidia,e-lpbk = <TEGRA_PIN_DISABLE>;
@@ -2834,4 +2834,3 @@ pinmux@ac281000 {
                drive {
                };
 };

sudo ./spidev_test -D /dev/spidev1.0 -s 500000 -v

英伟达是否在JetPack 7.0上测试过Thor芯片的SPI2功能？另外我并没有找到/sys/kernel/debug/tegra_pinctrl_reg这个路径

KevinFFF · December 5, 2025, 1:54am

Actually, this may be assigned dynamically according to the order of the driver probing during boot.

Could you share the full dmesg and device tree for further check?
Please also provide the result of ls -l /dev/spi* on your board.

BossOfNvidia · December 9, 2025, 7:11am

设备节点如下：

ls -l /dev/spi*
crw-rw---- 1 root gpio 153, 1 Jul  2  2025 /dev/spidev0.0
crw-rw---- 1 root gpio 153, 0 Jul  2  2025 /dev/spidev1.0
crw-rw---- 1 root gpio 153, 2 Jul  2  2025 /dev/spidev2.0
crw-rw---- 1 root gpio 153, 3 Jul  2  2025 /dev/spidev3.0

In addition, ，i see another post, Hasn’t aon been fully developed? The pins of spi2 belong to the aon domain. Is it possible that this is the reason why spi2 is not outputting waveforms?

KevinFFF · December 9, 2025, 8:25am

AON-GPIO on Thor is from ADSP.
It should still work.
Do you have the access for Jetpack 7.0 EA to verify?

I would also check the full dmesg to know the order of the probing.

BossOfNvidia · December 9, 2025, 8:42am

dmesg.txt (125.7 KB)
Please see the dmesg log.

BossOfNvidia · December 9, 2025, 8:54am

I see that c6c0000.spi is spi1.0 in sysfs

root@tegra-ubuntu:/sys/bus/platform/drivers/spi-tegra114/c6c0000.spi/spi_master# ls
spi1

KevinFFF · December 10, 2025, 6:44am

The order of the SPI probing is as following:

[   13.372698] spi-tegra114 c6c0000.spi: Adding to iommu group 44
[   13.807252] spi-tegra114 810c590000.spi: Adding to iommu group 46
[   14.588107] spi-tegra114 810c440000.spi: Adding to iommu group 49
[   15.169590] spi-tegra114 810c450000.spi: Adding to iommu group 52

As a result, c6c0000.spi should be /dev/spidev0.0 in this case.

Yes, the spi number here is fixed as following:
810c590000.spi → spi0
c6c0000.spi → spi1
810c440000.spi → spi2
810c450000.spi → spi3

BossOfNvidia · December 11, 2025, 2:55pm

问题原因找到了，实际上我测试的是SPI3(/dev/spidev2.0)，但是由于jetson agx thor devkit硬件上没有焊接电源芯片(J67)，导致U163无法工作，因此测试不到spi管脚波形，再次吐槽英伟达开发板偷工减料>_<。

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Jetson Thor SPI2对应哪个设备树节点？

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