Hi,
I’m trying to figured out what trace impedance should be used white DDR3 routung.
According to your stackup:
Trace 0.1mm has 50 Ohm SE
Trace 0.158 has 40 Ohm SE
DDR3 specification gives us examples of “Tree Architecture Without Series Resistors” on command and address lines. (the same as it is used in dev kit). Impedance of these traces should be 40 Ohm.
Data Bus traces should be 50Ohm.
As I understand:
Address lines should have 0.158mm
Data lines should have 0.1mm
Why in “Jetson TK1 Developer Kit Developer Board Design” track width are swapped? (Address: 0.1mm and Data: 0.158mm)
Thanks in advance
Jakub
Hi, as listed in tk1 embedded design guide, the range of impedance is +/-15%. The width of line is not fixed and is decided by impedance request, the thickness of dielectric and the custom layout.
Sorry, but it is not an answer to my question.
You’re writing about +/-15% impedance tolerance - so address lines which should have range of 34-46 Ohm are out of range, because have 0.1mm so gives us 50 Ohm.
My question is:
If I missing something or there is a mistake in track width on TK1 Developer Board?
Per design guide, the data signal group routing impedance is optional 40/50 ohm, and that of address/command lines is 50 ohm. Dev kit board is following that. The DDR chip on board is H5TC4G63AFR-RDA, I did not find the info that addr lines impedance is fixed to 40 ohm. The driver impedance of DDR IO is programmable, the dev kit is validated before ship out.