"Discrepancies" clarification between " NVIDIA Tegra K1 Embedded Platform Design Guide" and Jetson TK1 layout ?

Hi there,
We are working on TK1 design, based on “NVIDIA Tegra K1 Embedded Platform Design Guide” and its real layout, we found many discrepancies.
For example:
Table 23. DDR3L, 4x16 Data Signal Group Routing Requirements

  1. Trace Impedance DQ / DM DQS Single Ended DQS Differential
    40/50 (option) 45/50 (option) 80/90 (option)
    Ω ±15%. Options are for 40Ω/45Ω/80Ω or 50Ω/50Ω/90Ω
    Question1: In real Jetson TK1 layout, we noticed the same trace’s width isn’t even, is it allowed? We supposed the same trace should have the same width for impedance controlling purpose.
  2. Max Number of Vias (Tx to Rx (Per device) / Tx to all loads): 2.
    Questions 2: In real Jetson TK1 layout, some traces have vias but some haven’t, is it ok? We supposed they are better to be same without vias or with max 2 vias.
  3. Max Trace Length/Delay (PCB Main Trunk) 33.34 (210) mm (ps)
    Questions3 : in real Jetson TK1 layout, some traces is around 24mm, but some are 33mm; is it ok? We supposed they are better to be the same length.

Table 25. DDR3L, 4x16 Address/Command Signal Routing Requirements
4. Max Trace Length/Delay (PCB Main Trunk) 41.28 (260) mm (ps)
Questions 4 : in real Jetson TK1 layout, some traces is more than 60mm; is it ok? We supposed they are better to be less than 41.28 and follow the guidance.

Generally, want to know which we need to follow for our design, thanks for quick advice.

Best regards
George

Hi geo,

  1. Trace width is to follow impedance control, so not even is ok
  2. vias is less than 2 is must, and sure it is better if you can do it without vias.
  3. Max trace is must, but more important is to follow skew matching, if skew matching is in the range, that will be ok.
  4. PCB Main Trunk is part of whole trace, there are brunch length should be considered.

Hi Trumany,

Thank you very much. We will follow the design guides to design our own boards.

best regards
George