Controlled Impedance Tracing for TX1

Robotics & Edge Computing Jetson & Embedded Systems Jetson TX1
1

Hi there everyone,

I’m in the process of designing a customised carrier board for the TX1 and cutting off all the things our application doesn’t need. Some things though we do need like Ethernet, HDMI, and USB 3.0, which all require controlled impedance tracing.

In reading through the reference schematics for the nVidia Carrier Board though I’m a bit confused about a few things:

  • The impedance of the ethernet and hdmi pairs is listed as "GENERIC_DEZ1", what does this mean and what are the trace width/gap specifications for this?
  • Only 90 and 95 ohm impedance trace sizing are specified in the layer stack specification, for ethernet 100 ohm is required as per the OEM design guide and ethernet standards, is this not used by nVidia? (the TK1 board used 90ohm +/- 15% for ethernet for example)

Any insight on these design specs would be great, I’ve been banging away at the docs for a while now but can’t find the information I need.

Cheers!

2

Hi jazza,

GENERIC_DEZ1 means generic differential edge-coupled impedance, it claims these lines should follow differential lines routing rules.

Impedance value in stack spec is based on the given reference layer (top & below) and line width/gap, it is just for you reference not for specific lines, and so diff 100ohm of HDMI lines can be achieved by adjusting line width/gap.