Ethernet connector for custom carrier board


I’m having a lot of trouble finding an Ethernet connector with the same internal transformer structure as the one suggested on the Design Guide, and I need help specifying a replacement.

The Design Guide suggests this:


However I can’t find anything like this on Digikey/Mouser/Arrow.

Searching other posts I found an user showing this:


Is this type acceptable? Digikey has several 10/100/1000 Base-T and 1G Base-T connectors, but none with a similar transformer structure as the one on the Design Guide. Does anyone has a recommendation?


Hi, you can choose based on the characters as stated in this topic: NX Ethernet Magnetics?

Thanks for your reply. I see the characteristics on that post, but the biggest issue is finding a connector with the same internal transformer configuration as that one on the post you mentioned. I can find several 10/100/1000 Base-T and 1G Base-T connectors with different transformer configurations, but I’m not sure if they’re compatible with Jetson Nano.

What are my transformer configuration options? Does it have to be exactly like the one integrated in RJ45 conn of NX (A70-112-331N126)?


You can also choose a separated one like M3295NL used in P2597.

I see that the transformer configuration on M3295NL is very very different from the one mentioned on the Jetson Nano Design Guide, and even from the one on the topic you posted (NX Ethernet Magnetics?). Will that be compatible with Jetson Nano? I’m really not an expert on Ethernet, so these different transformer configurations simply seems incompatible to me.

For future readers, I found an ethernet connector with internal magnetics that matches the one on the Jetson Nano (A70-112-331N126) exactly, and it can be found easily on Digikey and Mouser. Its the 2337992-8 from TE Connectivity.

It matches it even mechanically. It’s a direct replacement.

I’ve successfully used both of these on Nano carrier boards:
Bel 0826-1X1T-GH-F
Pulse JW0-0006NL

Once I test mine I’ll post the results here. But do you think the one I mentioned will work?

I’m no authority, but yes, I’d expect that to work. It’s Ethernet, so unless you really mess up it’s just going to negotiate down in speed. If you really want to hedge your bets, find one with independent center taps on each pair and DNF a bunch of termination options that you could tweak afterwards:

One can also put footprints for pull-up resistors and ferrite beads on the high sides to some bias voltage too. Not sure of the levels on the Nano (1V?).

But I’ve never needed to populate any of these and get GbE link speeds just fine. Of course, all the normal advice - watch your layout, try to follow the design guides, actually do some diff-pair calculations for your PCB layer stack, match lengths, etc. The only issue I’ve ever had with the Nano module’s Ethernet is when I put an A02 module on a B01 carrier and scratched my head for two days wondering why it wouldn’t even link.

Thanks for your advice. I’ll definitely follow the instructions on the design guide.

By the way, Ethernet on the Jetson Nano is really simply this? Am I doing it correctly?

Yes, it’s that simple. Add some series 0402 or smaller 100nF caps or 0R resistors to each line if you want to spice it up, but this should be fine as-is.

Well, the design guide says this about the ethernet MDI traces:

Trace impedance - Diff pair / Single Ended:
Required: 100 / 50Ω ±15%. Differential impedance target is 100Ω. 90Ω can be used if 100Ω is not achievable.

I did route the MDI signals worrying about the differential pair, but not about their impedance, like this:

Should I really be concerned about the impedance of those differential pairs? The design guide seems pretty firm when it says “90Ω is acceptable if 100Ω is not achievable”.

The short answer is, yes, impedance matching is important in high-speed signaling.

Realistically though, just spin the board and cross your fingers as it will probably be just fine. In my experience, Ethernet transceivers are pretty forgiving and that’s reflected in the 100Ω/90Ω flexibility shown in the design guide here.

Here’s the design rules I used on my last carrier for the Ethernet diff-pairs:

This was specified on this layer stack, which is what PCBWay say they usually do on a standard option 4-layer board:

What’s the actual pair impedance for nominal signaling frequencies? I have no idea. Plug it in to 10 different calculators and you’ll get numbers from maybe 75Ω to like 160Ω. But it works great, so the test equipment can stay away for now.

So this trace impedance of the differential pair that the design guide mentions only depend on the trace parameters such as gap, width, thickness and dielectric constant of the board? Not on the length of the traces itself? Is that the characteristic impedance?

Yes, those are the dominant parameters and we are talking about characteristic impedance. Note that the thickness is the distance to the return path (ground plane), which might not be obvious.

Trace lengths & their limitations are independent of this calculation.

I tried in so many ways to get close to the required characteristic impedance of 100 ohms, but the best I can get is ~147 ohms, which would require 10 mils wide traces separated 4 mils.

Now, what I don’t understand is this: Looking at the Jetson Nano Development Kit gerber files, those same traces are like this:

They’re 4 mils wide and spaced 7 mils apart. Unless they have a very thin PCB with a very very high dielectric constant, no way they’re getting 100 ohms. With those traces, they’d need a 1 mm thick PCB with a dielectric constant of 15.

So, my questions are:

  1. Does that PCB (1 mm thick with 15 Dk) even exist? Am I missing something that they might have done to get to the required characteristic impedance of 100 ohms with those traces?

  2. If I increase my traces width from 5 to 8 mils, I get a 15 ohms reduction on the characteristic impedance. Is it worth it? That’d be 2x wider than the traces on the Jetson Nano Development Kit, and I never seen wide traces carrying high speed signals, so it concerns me.


PS: I see that their GND and VDD planes are on the inner layers. That would change the thickness of the board when calculating the impedance. However, still it’d require a large dielectric constant, even with the GND plane very close to the traces. But can this be the answer?

  1. … Am I missing something that they might have done to get to the required characteristic impedance of 100 ohms with those traces?

Yes, you are missing something fundamental in your calculations. You hinted that you thought it was the inner layers and that was the correct line of inquiry. The numbers you’ve indicated from the dev board seem pretty plausible to me:

  1. If I increase my traces width from 5 to 8 mils, I get a 15 ohms reduction on the characteristic impedance. Is it worth it? That’d be 2x wider than the traces on the Jetson Nano Development Kit, and I never seen wide traces carrying high speed signals, so it concerns me.

Look at my post above. I’ve got ~9mil traces on that board and this works just fine.

Are you trying to get these numbers on a 2-layer board? That might make it hard. I’m not even sure how well the models for edge coupled striplines hold up when you move to a geometry with the height being a large multiple of the spacing and trace width. Good luck.

But in your simulation you need the inner ground layer spaced ~4 mils from the top layer. Yes, I inserted this spacing (H=4 mils, or 0.11 mm) into my impedance calculator and it got to the right impedance, but is that even possible? Such small distance between layers?

Yes. All the time. See my previous post where I said that I used this exact layer stack and that those numbers work in real-world use.

Oh wow, yes I see on this website 0.11 mm between layers. Thanks PCRobert! I believe this solves this impedance problem! I’ll definitely do that then.

Just one question: The bottom layer on your simulation (the reference layer for H) has to be GND, right?