Hi Trumany,
Thank you for following up. Please see my two part response below.
Power supply investigation
When this problem first occured, I also suspected the power supply to be the cause, however, I was able to rule this out via the following troubleshooting process:
- First, I switched to a 12V 84A power supply and tested again, but the crash still occured.
- During the crash, I measured the output of our TPS54561 regulator which directly sources our SoM power sequencer (shown below). It remained at ~4.9V despite the SoM shutting down.
- I then checked
PWR_EN and found that it was 0V. This indicated that power was being disconnected from the SoM, even though the power supply remained steady.
- Only two inputs remained that could cause the system to shut down;
SHUTDOWN_REQ, and PWR_GOOD. PWR_GOOD is normally sourced from the TPS54561 regulator, however the resistor (R68) is unpopulated, so it has no effect. This indicated that SHUTDOWN_REQ must have been the cause of the shutdown.
- I checked
SHUTDOWN_REQ and confirmed that it was being pulled low during the crash.
This investigation confirmed that the power supply was not failing, however, it was possible that the Jetson PMIC was detecting unstable power and asserting SHUTDOWN_REQ as a precaution.
To improve stability under heavy loads, I added 3 x 300μf Tan-poly capacitors to our SoM input voltage rail. The SoM was able to remain powered for a few additional milliseconds, but SHUTDOWN_REQ was still asserted eventually, causing a shutdown.
To summarize, the crash was not caused by loss of power from the power supply, but rather from SHUTDOWN_REQ being pulled low and disabling output from our SoM power sequencer. This was what prompted me to inquire about the cause of the SHUTDOWN_REQ assertion.
Power down timing
the reset reason is TEGRA_POWER_ON_RESET sounds like a a normal reboot.
If SHUTDOWN_REQ was pulled low, but TEGRA_POWER_ON_RESET indicates a normal reboot, does that imply that the TEGRA_POWER_ON_RESET value isn’t being updated correctly?
Figure 5-5, page 16 of the Jetson Xavier NX Product Design Guide shows that VDD_IN must be allowed no less than 10ms to decay from 5V to 3V, however, as shown below, this is occuring in less than 2ms in our system.
Jetson Xavier NX Product Design Guide:
Figure 5-5, page 16. Power Down (Sudden Power Loss)
Our system
Perhaps the design isn’t allowing enough time for the shutdown procedure to occur, resulting in failure to update the value of TEGRA_POWER_ON_RESET. Do you think this could be the case?
