MIPI CSI Lane Frequency & Signal Integrity Concerns on Custom AGX Orin Carrier

Robotics & Edge Computing Jetson & Embedded Systems Jetson AGX Orin
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I’m designing a custom carrier board for AGX Orin. The D457 GMSL camera connects to a GMSL deserializer, which then interfaces with the AGX Orin via MIPI CSI lanes.

I need help calculating the maximum frequency of the MIPI CSI lanes after the GMSL deserializer.

From what I understand, AGX Orin uses a custom stackup, and some PCB manufacturers struggle to produce it. Additionally, the design includes buried vias with controlled impedance calculations. Given these challenges, I’m concerned about signal integrity, especially for MIPI CSI after fabrication.

What is the maximum lane speed (GHz) the PCB should support? Do you have any recommendations for maintaining signal integrity in this scenario?

4

There is no update from you for a period, assuming this is not an issue anymore.
Hence, we are closing this topic. If need further support, please open a new one.
Thanks ~0409

Do you check the design guide?