AGX Orin Carrier Board - MIPI CSI Lane Length Matching

[electronxx]

Hello,

I am designing a carrier board for AGX Orin and have some questions regarding MIPI CSI length matching.

• For example, for CSI 0:
  • CSI_0_D0_P / CSI_0_D0_N
  • CSI_0_CLK_P / CSI_0_CLK_N
  • CSI_0_D1_P / CSI_0_D1_NI match all these lanes within themselves.
• Similarly, for CSI 1:
  • CSI_1_D0_P / CSI_1_D0_N
  • CSI_1_CLK_P / CSI_1_CLK_N
  • CSI_1_D1_P / CSI_1_D1_NI match all these lanes within themselves.
• When analyzing the reference design’s trace lengths, I noticed the following grouping:
  • CSI0 is matched with CSI1
  • CSI2 is matched with CSI3
  • CSI4 is matched with CSI5
  • CSI6 is matched with CSI7

In this case, do I also need to match the lengths between different CSI groups, such as CSI0 and CSI1?
Or should each CSI group only be matched internally?

Thanks.

[sgursal]

To support x4 lane Camera Configurations the net length matching as you have observed is required. Refer to Jetson AGX Orin Series Design Guide for supported x4 lane camera configurations. Refer to 10.1 CSI D-PHY Design Guidelines and 10.2 CSI C-PHY Design Guidelines Log in | NVIDIA Developer