Hi,
We are trying to acquire some images from a FPGA by using the MIPI interface of the Xavier NX. The FPGA sends a 640x480,16 bit test pattern to the NX. From NX perspective we are considering a 1280x480 format to be compatible with RAW8 format. We made the following changes to get it working:
- DTS changes. We are consider the IMX219 dts as a starting point for FPGA support. You can find the configuration below:
mode2 {
mclk_khz = "24000";
num_lanes = [32 00];
tegra_sinterface = "serial_a";
phy_mode = "DPHY";
discontinuous_clk = "yes";
dpcm_enable = "false";
cil_settletime = [30 00];
active_w = "1280";
active_h = "480";
pixel_t = "bayer_rggb";
readout_orientation = "90";
line_length = "2780";
inherent_gain = [31 00];
mclk_multiplier = "9.33";
pix_clk_hz = "100000000";
serdes_pix_clk_hz = "535000000";
gain_factor = "16";
framerate_factor = "1000000";
exposure_factor = "1000000";
min_gain_val = "16";
max_gain_val = "170";
step_gain_val = [31 00];
default_gain = "16";
min_hdr_ratio = [31 00];
max_hdr_ratio = [31 00];
min_framerate = "20000000";
max_framerate = "60000000";
step_framerate = [31 00];
default_framerate = "50000000";
min_exp_time = "13";
max_exp_time = "683709";
step_exp_time = [31 00];
default_exp_time = "2495";
embedded_metadata_height = "0";
};
- Kernel changes. We remove the I2C part from the sensor kernel driver and we modify the file nvidia/drivers/media/platform/tegra/camera/vi/capture.c to not wait the
capture_resp. In this way, the Xavier starts the frame capture without I2C handshake. Moreover, we have changed thecamera_common_frmfmt imx219_frmfmstructure to be compatible with the new format 1280x480.
static const struct camera_common_frmfmt imx219_frmfmt[] = {
{{3264, 2464}, imx219_21fps, 1, 0, IMX219_MODE_3264x2464_21FPS},
/* Add modes with no device tree support after below */
{{3264, 1848}, imx219_28fps, 1, 0, IMX219_MODE_3264x1848_28FPS},
{{1280, 480}, imx219_30fps, 1, 0, IMX219_MODE_1280x480_30FPS},
{{1280, 720}, imx219_60fps, 1, 0, IMX219_MODE_1280x720_60FPS},
{{1280, 720}, imx219_120fps, 1, 0, IMX219_MODE_1280x720_120FPS},
};
- RCE fw has been updated to remove ECC/CRC check as described in this post. We are using Jetpack 4.4.1 to be compatible with RCE fw.
We are facing an issue since v4l2 can only acquire few frames before blocking. Here is the v4l2 command with the dmesg output:
v4l2-ctl -d /dev/video0 --set-fmt-video=width=1280,height=480,pixelformat=RGGB --set-ctrl bypass_mode=0,sensor_mode=2 --stream-mmap --stream-count=5
[ 3654.472372] [RCE] vi5_hwinit: firmware CL2018101701 protocol version 2.2
[ 3654.472388] [RCE] error config mask = 3
[ 3654.472396] [RCE] nvcsi_stream_apply_error_config stream_intr_mask ECC/CRC = 3
[ 3654.472413] tegra194-vi5 15c10000.vi: corr_err: discarding frame 56128, flags: 0, err_data 0
[ 3654.481264] tegra194-vi5 15c10000.vi: corr_err: discarding frame 0, flags: 0, err_data 0
[ 3654.489179] tegra194-vi5 15c10000.vi: corr_err: discarding frame 0, flags: 0, err_data 0
[ 3654.497290] tegra194-vi5 15c10000.vi: corr_err: discarding frame 0, flags: 0, err_data 0
[ 3654.505749] tegra194-vi5 15c10000.vi: corr_err: discarding frame 56129, flags: 0, err_data 0
[ 3654.514334] tegra194-vi5 15c10000.vi: corr_err: discarding frame 0, flags: 0, err_data 0
[ 3654.522610] tegra194-vi5 15c10000.vi: corr_err: discarding frame 0, flags: 0, err_data 0
[ 3654.530624] [RCE] ERROR: capture-scheduler.c:2375 [capture_scheduler_thread] "Error processing event 0x100000"
[ 3654.530644] tegra194-vi5 15c10000.vi: corr_err: discarding frame 0, flags: 0, err_data 0
[ 3654.538864] tegra194-vi5 15c10000.vi: corr_err: discarding frame 0, flags: 0, err_data 0
[ 3654.546621] tegra194-vi5 15c10000.vi: corr_err: discarding frame 0, flags: 0, err_data 0
[ 3654.555008] tegra194-vi5 15c10000.vi: corr_err: discarding frame 0, flags: 0, err_data 0
[ 3654.562983] tegra194-vi5 15c10000.vi: corr_err: discarding frame 0, flags: 0, err_data 0
[ 3654.571206] tegra194-vi5 15c10000.vi: corr_err: discarding frame 0, flags: 0, err_data 0
[ 3654.578990] tegra194-vi5 15c10000.vi: corr_err: discarding frame 0, flags: 0, err_data 0
[ 3654.587338] tegra194-vi5 15c10000.vi: corr_err: discarding frame 0, flags: 0, err_data 0
[ 3654.595089] tegra194-vi5 15c10000.vi: corr_err: discarding frame 0, flags: 0, err_data 0
[ 3654.603555] tegra194-vi5 15c10000.vi: corr_err: discarding frame 0, flags: 0, err_data 0
[ 3654.611369] tegra194-vi5 15c10000.vi: corr_err: discarding frame 0, flags: 0, err_data 0
[ 3654.619860] tegra194-vi5 15c10000.vi: corr_err: discarding frame 0, flags: 0, err_data 0
[ 3654.695797] [RCE] error config mask = e59ff018
[ 3654.695874] [RCE] nvcsi_stream_apply_error_config stream_intr_mask ECC/CRC = 0
Checking the trace log, it shows the following output:
rtcpu_nvcsi_intr: tstamp:3600903419 class:GLOBAL type:STREAM_VC phy:0 cil:0 st:0 vc:0 status:0x00000004
rtcpu_nvcsi_intr: tstamp:3600903419 class:CORRECTABLE_ERR type:STREAM_VC phy:0 cil:0 st:0 vc:0 status:0x00000004
rtcpu_nvcsi_intr: tstamp:3600905158 class:GLOBAL type:STREAM_VC phy:0 cil:0 st:0 vc:0 status:0x00000004
rtcpu_nvcsi_intr: tstamp:3600905158 class:CORRECTABLE_ERR type:STREAM_VC phy:0 cil:0 st:0 vc:0 status:0x00000004
rtcpu_nvcsi_intr: tstamp:3600906896 class:GLOBAL type:STREAM_VC phy:0 cil:0 st:0 vc:0 status:0x00000004
rtcpu_nvcsi_intr: tstamp:3600906896 class:CORRECTABLE_ERR type:STREAM_VC phy:0 cil:0 st:0 vc:0 status:0x00000004
rtcpu_nvcsi_intr: tstamp:3600908641 class:GLOBAL type:STREAM_VC phy:0 cil:0 st:0 vc:0 status:0x00000004
rtcpu_nvcsi_intr: tstamp:3600908641 class:CORRECTABLE_ERR type:STREAM_VC phy:0 cil:0 st:0 vc:0 status:0x00000004
rtcpu_nvcsi_intr: tstamp:3600910372 class:GLOBAL type:STREAM_VC phy:0 cil:0 st:0 vc:0 status:0x00000004
rtcpu_nvcsi_intr: tstamp:3600910372 class:CORRECTABLE_ERR type:STREAM_VC phy:0 cil:0 st:0 vc:0 status:0x00000004
rtcpu_nvcsi_intr: tstamp:3600912108 class:GLOBAL type:STREAM_VC phy:0 cil:0 st:0 vc:0 status:0x00000004
rtcpu_nvcsi_intr: tstamp:3600912108 class:CORRECTABLE_ERR type:STREAM_VC phy:0 cil:0 st:0 vc:0 status:0x00000004
rtcpu_nvcsi_intr: tstamp:3600913846 class:GLOBAL type:STREAM_VC phy:0 cil:0 st:0 vc:0 status:0x00000004
rtcpu_nvcsi_intr: tstamp:3600913846 class:CORRECTABLE_ERR type:STREAM_VC phy:0 cil:0 st:0 vc:0 status:0x00000004
rtcpu_nvcsi_intr: tstamp:3600915583 class:GLOBAL type:STREAM_VC phy:0 cil:0 st:0 vc:0 status:0x00000004
rtcpu_nvcsi_intr: tstamp:3600915583 class:CORRECTABLE_ERR type:STREAM_VC phy:0 cil:0 st:0 vc:0 status:0x00000004
rtcpu_nvcsi_intr: tstamp:3600917322 class:GLOBAL type:STREAM_VC phy:0 cil:0 st:0 vc:0 status:0x00000004
rtcpu_nvcsi_intr: tstamp:3600917322 class:CORRECTABLE_ERR type:STREAM_VC phy:0 cil:0 st:0 vc:0 status:0x00000004
rtcpu_nvcsi_intr: tstamp:3600919057 class:GLOBAL type:STREAM_VC phy:0 cil:0 st:0 vc:0 status:0x00000004
rtcpu_nvcsi_intr: tstamp:3600919057 class:CORRECTABLE_ERR type:STREAM_VC phy:0 cil:0 st:0 vc:0 status:0x00000004
rtcpu_nvcsi_intr: tstamp:3600920795 class:GLOBAL type:STREAM_VC phy:0 cil:0 st:0 vc:0 status:0x00000004
rtcpu_nvcsi_intr: tstamp:3600920795 class:CORRECTABLE_ERR type:STREAM_VC phy:0 cil:0 st:0 vc:0 status:0x00000004
rtcpu_nvcsi_intr: tstamp:3600922536 class:GLOBAL type:STREAM_VC phy:0 cil:0 st:0 vc:0 status:0x00000004
rtcpu_nvcsi_intr: tstamp:3600922536 class:CORRECTABLE_ERR type:STREAM_VC phy:0 cil:0 st:0 vc:0 status:0x00000004
rtcpu_nvcsi_intr: tstamp:3600924271 class:GLOBAL type:STREAM_VC phy:0 cil:0 st:0 vc:0 status:0x00000004
rtcpu_nvcsi_intr: tstamp:3600924271 class:CORRECTABLE_ERR type:STREAM_VC phy:0 cil:0 st:0 vc:0 status:0x00000004
rtcpu_nvcsi_intr: tstamp:3600926009 class:GLOBAL type:STREAM_VC phy:0 cil:0 st:0 vc:0 status:0x00000004
rtcpu_nvcsi_intr: tstamp:3600926009 class:CORRECTABLE_ERR type:STREAM_VC phy:0 cil:0 st:0 vc:0 status:0x00000004
rtcpu_nvcsi_intr: tstamp:3600927749 class:GLOBAL type:STREAM_VC phy:0 cil:0 st:0 vc:0 status:0x00000004
rtcpu_nvcsi_intr: tstamp:3600927749 class:CORRECTABLE_ERR type:STREAM_VC phy:0 cil:0 st:0 vc:0 status:0x00000004
rtcpu_nvcsi_intr: tstamp:3600929485 class:GLOBAL type:STREAM_VC phy:0 cil:0 st:0 vc:0 status:0x00000004
rtcpu_nvcsi_intr: tstamp:3600929485 class:CORRECTABLE_ERR type:STREAM_VC phy:0 cil:0 st:0 vc:0 status:0x00000004
rtcpu_nvcsi_intr: tstamp:3600931224 class:GLOBAL type:STREAM_VC phy:0 cil:0 st:0 vc:0 status:0x00000004
rtcpu_nvcsi_intr: tstamp:3600931224 class:CORRECTABLE_ERR type:STREAM_VC phy:0 cil:0 st:0 vc:0 status:0x00000004
rtcpu_nvcsi_intr: tstamp:3600932960 class:GLOBAL type:STREAM_VC phy:0 cil:0 st:0 vc:0 status:0x00000004
rtcpu_nvcsi_intr: tstamp:3600932960 class:CORRECTABLE_ERR type:STREAM_VC phy:0 cil:0 st:0 vc:0 status:0x00000004
Is the Xavier NX device tree correctly configured? Why are we able to only acquire few frames? May it be an hardware issue? Is there a synchronization/clock problem?
Any hints? @ShaneCCC?
Thank you.