Jetson Xavier NX issue grabbing MIPI CSI stream from FPGA

[jdiegodelgado]

@borjabasket14 ,

The only thing that make sense to me is what they discuss in this post:

MIPI issue between FPGA and Xavier NX

We have reduced the frame rate but the problem persists. My idea is that we have a data misalignment due to bad timing. May this concern be correct? Moreover, our FPGA design supports 4 different modes for MIPI clock: Continuous mode: the clock on the clock lane is running all the time Non-Continuous mode: the clock stops and the clock lane enters Stop-State between every CSI-2 packet Frame-Continuous mode: the clock lane is running during all packets of a frame, from Frame Start packet, thro…

“The FPGA continuously sends the images via MIPI interface without the possibility of controlling the stream (e.g., no start/stop). This probably causes errors at the Xavier side.”

Maybe, try to:

discontinuous_clk = "yes";

JDiego Delgado
Embedded SW Engineer at RidgeRun
Contact us: support@ridgerun.com
Developers wiki: https://developer.ridgerun.com/
Website: www.ridgerun.com

Best,