We have reduced the frame rate but the problem persists. My idea is that we have a data misalignment due to bad timing. May this concern be correct?
Moreover, our FPGA design supports 4 different modes for MIPI clock:
- Continuous mode: the clock on the clock lane is running all the time
- Non-Continuous mode: the clock stops and the clock lane enters Stop-State between every CSI-2 packet
- Frame-Continuous mode: the clock lane is running during all packets of a frame, from Frame Start packet, through all the long packets with video line data, until the Frame End packet. After the Frame End packet, the clock lane stops and enters Stop-State
- Line-Continuous mode, the clock lane keeps running between a Frame Start packet and the first long packet with video line data. The clock lanes stops after all long packets and after Frame End packet.
Which is the correct configuration for the MIPI Xavier receiver? In the device tree, discontinuous_clk=yes thus we are considering the clock in non-continuous mode.
Thank you