MIPI timing and signal startup sequence


Continuing the discussion from MIPI port identification between HW and SW, we received further input from the hardware engineers and questions to address.

In page 675 of the Xavier Series SoC TRM we find this waveform:

Referring to the figure above:

  1. Is the requirement that the lanes, after reset, will go through LP00-LP10-LP11 a must? According to them it is not part of the MIPI DPHY or CSI2 standards. If it is a must, can the camera processor handle sensors that do not adhere to this requirement (e.g., go through LP00-LP11, or go directly to LP 11)?
  2. Can t5 and t7 specified exactly? How are they configured? (via cil_settletime?)


hello moti4,

  1. LP sequence it should follow by LP11->LP01->LP00->LP11 for entering high-speed.
  2. there’s tune-able variable for t8, please see-also developer guide for cil_settletime, it’s configuration for THS settle time of the MIPI lane.
  3. we don’t have parameter setting for t7, however, it’s the initial timing before s_stream operations. you may try adding some delay within kernel driver for extension t7.

Thank you @JerryChang for the answer.
So if I understand correctly, the LP sequence enclosed by t8 is defined entirely by cil_settletime and there is no further breakdown into specific timings of t5, t6 etc.?

Is this a correct statement? (with the conclusion that once the driver defines the correct cil_settletime value in the device tree, the nvcsi core should be able to parse the incoming packets as long as they conform to the LP sequence)
Does it apply in the same way to clock and data channels?

Kind regards,

as mentioned…

this is configuration for how many csicil clock cycles to wait after LP00 for data-lane.
clock-lane usually used constant value for waiting.
you may see-also TRM by checking CLK_SETTLE and THS_SETTLE for more details.

Great @JerryChang, thank you for the additional details, we’ll look deeply into that.

One last note, regarding the initial LP00 → LP10 transition, can you share where to look for further information in the MIPI CSI standard (assuming it’s v1.2)?

Kind regards,

please refer to… MIPI Alliance Specification for D-PHY, Version 2.1

Thank you very much @JerryChang, Ill forward this information to the engineers.

Hi @JerryChang,

We’ve managed to find the relevant figure from the TRM document in the mipi Camera Command Set (CCS 1.0) standard on page 17.
Can you share what subset of commands are mandatory to be implemented? Or where in the kernel code to look for them?
(Just in case a correct startup sequence depends on these commands to be sent from the camera to the receiver).

Happy new year :-),

hello moti4,

I assume you’re working with jetson-linux-r3541 release version.
please download [Driver Package (BSP) Sources] package for the public release sources.
you’ll need to extract kernel_src.tbz2 package, and please check device tree sources for the cil_settletime property.
for example,

please also check sensor programming guide, Sensor Software Driver Programming.

Thank you @JerryChang, I’ll look deeper into it.
As a matter of fact, it’s an older jetpack (4.6.1), but I assume we should follow the same path.

Kind regards,

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