Hi, Following up from previous posts, we managed to get some live signal reporting during a v4l2 stream. Our HW design follows the one for ov5693, such that physical connectivity is through CSI2 port. The original dtsi file stated: tegra_sinterface = "serial_c"; Can changing the definition …

[image] moti4: Is it correct to state that intr_cil_data_lane_sot_mb_err1_a represents an error in lane 1, whereas intr_cil_data_lane_sot_mb_err0_a is the respective register for lane 0? yes. intr_cil_data_lane_sot_mb_err1_a it means one bit error has detected on the data-lane 1 sync word.

MIPI port identification between HW and SW

Robotics & Edge Computing Jetson & Embedded Systems Jetson AGX Xavier

JerryChang November 8, 2023, 2:25am 5

yes. intr_cil_data_lane_sot_mb_err1_a it means one bit error has detected on the data-lane 1 sync word.

MIPI timing and signal startup sequence

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MIPI port identification between HW and SW

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