Hello All,
In nvcsi, it is configured to
csi-port=2
bus-width = 4
In csi4_start_streaming ports(), printing the PHY status registers:
CILB_INTR_STATUS 0x00000088
CILB_ERR_INTR_STATUS 0x00000088
In phy registers, What is the meaning of these bits:
bit 3: intr_cil_data_lane_ctrl_err0_b
bit 7: intr_cil_data_lane_ctrl_err1_b
registers name:
NVCSI_PHY_0_CILB_INTR_STATUS_CILB_0,
NVCSI_PHY_0_CILB_ERR_INTR_STATUS_CILB_0
-Thanks.
hello BalajiNP,
you may also refer to [url]https://elinux.org/Jetson_TX2_Camera_BringUp[/url] for some debug tips.
thanks
Hello JerryChang,
Thanks for the reply.
The main query is: Need the nvcsi registers related details.
Please check the comment #1.
-Thanks.
hello BalajiNP,
please download [Tegra X2 (Parker Series SoC) Technical Reference Manual] from Jetson Download Center, you should check these registers at [MIPI CAMERA SERIAL INTERFACE (CSI)] chapter for more details.
thanks
Hello JerryChang,
In TRM document, the below details are not there:
Registers name:
NVCSI_PHY_0_CILB_INTR_STATUS_CILB_0,
NVCSI_PHY_0_CILB_ERR_INTR_STATUS_CILB_0
register fields:
2-bit: intr_cil_data_lane_sot_mb_err0_b
3-bit: intr_cil_data_lane_ctrl_err0_b
.
.
6-bit: intr_cil_data_lane_sot_mb_err1_b
7-bit: intr_cil_data_lane_ctrl_err1_b
In what scenarios, the above bits set?
-Thanks.
hello BalajiNP,
please check [Chapter 28: MIPI Camera Serial Interface (CSI)] and you should found the register descriptions in [28.6 MIPI-CSI Registers],
there’s session for NVCSI_PHY_0_CILB_INTR_STATUS_CILB_0 in [28.6.251 NVCSI_PHY_0_CILB_INTR_STATUS_CILB_0].
also, the description of NVCSI_PHY_0_CILB_ERR_INTR_STATUS_CILB_0 is in [28.6.253 NVCSI_PHY_0_CILB_ERR_INTR_STATUS_CILB_0]
these were CSI debug registers, please also refer to kernel sources about the usage.
<top>/kernel_src/kernel/kernel-4.4/drivers/media/platform/tegra/camera/csi/csi4_fops.c
<top>/kernel_src/kernel/kernel-4.4/drivers/media/platform/tegra/camera/csi/csi4_registers.h