MIPI port identification between HW and SW

Robotics & Edge Computing Jetson Systems Jetson AGX Xavier
1

Hi,

Following up from previous posts, we managed to get some live signal reporting during a v4l2 stream.

Our HW design follows the one for ov5693, such that physical connectivity is through CSI2 port.
The original dtsi file stated:

				tegra_sinterface = "serial_c";

Can changing the definition to serial_a cause any trouble? (So that the serial interface is directly connected to the physical port)
Or the only relevant configuration between the dtsi and the physical port resides under vi {ports {port}} and nvcsi { channel {ports {port}}} subsections?

Currently, the response always returns the familiar (no other status code is present):

rtcpu_nvcsi_intr: .... class:CORRECTABLE_ERR type:PHY_INTR phy:1 cil:0 st:0 vc:0 status: 0x00000040
rtcpu_nvcsi_intr: .... class:GLOBAL type:PHY_INTR0 phy:1 cil:0 st:0 vc:0 status: 0x00000040

According to the TRM this means the bit intr_cil_data_lane_sot_mb_err1_a is on, but not for err0.
What can be the cause for this? (not both being set for example).
If that’s a hint to search for improper signal form.

Thanks,
Moti.

3

hello moti4,

please refer to this diagram, Port Index.
you may also check Camera Module Hardware Design Guide to review the schematic.

4

Hi @JerryChang,

Thank you very much for your response, we’ll look into it.

Is it correct to state that intr_cil_data_lane_sot_mb_err1_a represents an error in lane 1, whereas intr_cil_data_lane_sot_mb_err0_a is the respective register for lane 0?

Kind regards,
Moti.

5

yes. intr_cil_data_lane_sot_mb_err1_a it means one bit error has detected on the data-lane 1 sync word.

6

Thank you very much.
We’ll further investigate this.

Regards,
Moti.

8

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