Thank you very much! Yes, I have this setting in the configuration file, as
When I use “gpu_init_comms_via_cpu: 0”, the segmentation issue has been addressed, but the following new errors occur:
root@c_aerial_root:/opt/nvidia/cuBB# $cuBB_SDK/testBenches/phase4_test_scripts/run2_cuPHYcontroller.sh $RUN2_CUPHYCONTROLLER_PARAMS
stopping MPS for green contexts
Stopping MPS...
Cannot find MPS control daemon process
/opt/nvidia/cuBB build.10_04.x86_64 F08_GL4
/opt/nvidia/cuBB/build.10_04.x86_64/cuPHY-CP/cuphycontroller/examples/cuphycontroller_scf F08_GL4
F08_GL4
Started cuphycontroller on CPU core 19
05:47:42.336117 CON phy_init 0 [CTL.SCF] Config file: /opt/nvidia/cuBB/cuPHY-CP/cuphycontroller/config/cuphycontroller_F08_GL4.yaml
05:47:42.338573 CON phy_init 0 [CTL.SCF] low_priority_core=0
05:47:42.338596 CON phy_init 0 [APP.CONFIG] Current TAI offset: 0s
05:47:42.338651 CON phy_init 0 [NVLOG.CPP] Using /opt/nvidia/cuBB/cuPHY/nvlog/config/nvlog_config.yaml for nvlog configuration
05:47:42.354302 CON phy_init 0 [NVLOG.CPP] Output log file path /tmp/phy.log
Aerial metrics backend address: 127.0.0.1:60000
YAML invalid key: dlc_alloc_cplane_bfw_txq Using default value of 0 for YAML_PARAM_DLC_ALLOC_CPLANE_BFW_TXQ
05:47:42.368004 CON phy_init 0 [CTL.YAML] cuphycontroller config. yaml does not have ul_order_timeout_gpu_srs_ns key; defaulting to 5200000 ns
05:47:42.368021 WRN phy_init 0 [CTL.YAML] cuphycontroller config. yaml does not have ul_order_kernel_mode key; defaulting to 0 (Ping-Pong mode).
05:47:42.368111 WRN phy_init 0 [CTL.YAML] YAML invalid key: enable_l1_param_sanity_check Using default value of 0 to YAML_PARAM_ENABLE_L1_PARAM_SANITY_CHECK
05:47:42.368189 WRN phy_init 0 [CTL.YAML] YAML invalid key: pusch_weighted_average_cfo Using default value of 0 to PUSCH-WEIGHTED-AVERAGE-CFO
05:47:42.368217 WRN phy_init 0 [CTL.YAML] YAML invalid key: pucch_aggr_per_ctx Using default value of 4 to YAML_PARAM_PUCCH_AGGR_PER_CTX
05:47:42.368226 WRN phy_init 0 [CTL.YAML] YAML invalid key: srs_aggr_per_ctx Using default value of 2 to YAML_PARAM_SRS_AGGR_PER_CTX
05:47:42.368235 WRN phy_init 0 [CTL.YAML] YAML invalid key: ul_input_buffer_per_cell_srs Using default value of 4 to YAML_PARAM_UL_INPUT_BUFFER_NUM_PER_CELL_SRS
05:47:42.368244 WRN phy_init 0 [CTL.YAML] YAML invalid key: max_ru_unhealthy_ul_slots Using default value of 0 for YAML_PARAM_MAX_RU_UNHEALTHY_UL_SLOTS
05:47:42.368270 WRN phy_init 0 [CTL.YAML] YAML invalid key: ul_pcap_capture_enable Using default value of 0 for YAML_PARAM_UL_PCAP_CAPTURE_ENABLE
05:47:42.368280 WRN phy_init 0 [CTL.YAML] YAML invalid key: pcap_logger_ul_cplane_enable PCAP Logging parameters are set incorrectly, so logger is disabled by default
05:47:42.368333 WRN phy_init 0 [CTL.YAML] YAML invalid key: enable_tx_notification Using default value of 0 for YAML_PARAM_ENABLE_TX_NOTIFICATION
05:47:42.368456 WRN phy_init 0 [CTL.YAML] YAML invalid key: pusch_nMaxLdpcHetConfigs Using default value of 32 to PUSCH-N-MAX-LDPC-HET-CONFIGS
05:47:42.368538 CON phy_init 0 [CTL.YAML] cell_id 1 nic_index :0
05:47:42.368820 CON phy_init 0 [CTL.YAML] t1a_min_cp_dl_ns/t1a_max_cp_dl_ns not set in config file, using default t1a_min_cp_dl_ns = 419 us and t1a_max_cp_dl_ns = 669 us
05:47:42.368827 CON phy_init 0 [CTL.YAML] t1a_min_cp_ul_ns not set in config file, using default of 285 us
05:47:42.368947 CON phy_init 0 [CTL.YAML] Num Slots: 8
05:47:42.368948 CON phy_init 0 [CTL.YAML] Enable UL cuPHY Graphs: 1
05:47:42.368948 CON phy_init 0 [CTL.YAML] Enable DL cuPHY Graphs: 1
05:47:42.368948 CON phy_init 0 [CTL.YAML] Accurate TX scheduling clock resolution (ns): 500
05:47:42.368949 CON phy_init 0 [CTL.YAML] DPDK core: 0
05:47:42.368949 CON phy_init 0 [CTL.YAML] Prometheus core: -1
05:47:42.368950 CON phy_init 0 [CTL.YAML] UL cores:
05:47:42.368950 CON phy_init 0 [CTL.YAML] - 2
05:47:42.368950 CON phy_init 0 [CTL.YAML] - 3
05:47:42.368951 CON phy_init 0 [CTL.YAML] DL cores:
05:47:42.368951 CON phy_init 0 [CTL.YAML] - 4
05:47:42.368951 CON phy_init 0 [CTL.YAML] - 5
05:47:42.368951 CON phy_init 0 [CTL.YAML] - 6
05:47:42.368951 CON phy_init 0 [CTL.YAML] - 7
05:47:42.368951 CON phy_init 0 [CTL.YAML] Debug worker: 9
05:47:42.368952 CON phy_init 0 [CTL.YAML] Data Lake core: -1
05:47:42.368952 CON phy_init 0 [CTL.YAML] SRS starting Section ID: 3072
05:47:42.368952 CON phy_init 0 [CTL.YAML] PRACH starting Section ID: 2048
05:47:42.368952 CON phy_init 0 [CTL.YAML] USE GREEN CONTEXTS: 1
05:47:42.368952 CON phy_init 0 [CTL.YAML] USE BATCHED MEMCPY: 1
05:47:42.368952 CON phy_init 0 [CTL.YAML] MPS SM PUSCH: 32
05:47:42.368953 CON phy_init 0 [CTL.YAML] MPS SM PUCCH: 8
05:47:42.368954 CON phy_init 0 [CTL.YAML] MPS SM PRACH: 4
05:47:42.368954 CON phy_init 0 [CTL.YAML] MPS SM UL ORDER: 6
05:47:42.368954 CON phy_init 0 [CTL.YAML] MPS SM PDSCH: 40
05:47:42.368954 CON phy_init 0 [CTL.YAML] MPS SM PDCCH: 4
05:47:42.368955 CON phy_init 0 [CTL.YAML] MPS SM PBCH: 2
05:47:42.368955 CON phy_init 0 [CTL.YAML] MPS SM GPU_COMMS: 16
05:47:42.368955 CON phy_init 0 [CTL.YAML] MPS SM SRS: 14
05:47:42.368955 CON phy_init 0 [CTL.YAML] UL Order Kernel Mode: 0
05:47:42.368955 CON phy_init 0 [CTL.YAML] PDSCH fallback: 0
05:47:42.368955 CON phy_init 0 [CTL.YAML] Massive MIMO enable: 0
05:47:42.368956 CON phy_init 0 [CTL.YAML] mMIMO_enable feature 0
05:47:42.368956 CON phy_init 0 [CTL.YAML] Enable SRS : 0
05:47:42.368956 CON phy_init 0 [CTL.YAML] ul_order_timeout_gpu_log_enable: 1
05:47:42.368956 CON phy_init 0 [CTL.YAML] ue_mode: 0
05:47:42.368956 CON phy_init 0 [CTL.YAML] Aggr Obj Non-availability threshold: 5
05:47:42.368956 CON phy_init 0 [CTL.YAML] sendCPlane_timing_error_th_ns: 0
05:47:42.368956 CON phy_init 0 [CTL.YAML] pusch_aggr_per_ctx: 4
05:47:42.368957 CON phy_init 0 [CTL.YAML] prach_aggr_per_ctx: 2
05:47:42.368957 CON phy_init 0 [CTL.YAML] pucch_aggr_per_ctx: 4
05:47:42.368957 CON phy_init 0 [CTL.YAML] srs_aggr_per_ctx: 2
05:47:42.368957 CON phy_init 0 [CTL.YAML] max_harq_pools: 128
05:47:42.368957 CON phy_init 0 [CTL.YAML] max_harq_tx_count_bundled: 10
05:47:42.368957 CON phy_init 0 [CTL.YAML] max_harq_tx_count_non_bundled: 4
05:47:42.368957 CON phy_init 0 [CTL.YAML] ul_input_buffer_per_cell: 5
05:47:42.368958 CON phy_init 0 [CTL.YAML] ul_input_buffer_per_cell_srs: 4
05:47:42.368958 CON phy_init 0 [CTL.YAML] max_ru_unhealthy_ul_slots: 0
05:47:42.368958 CON phy_init 0 [CTL.YAML] srs_chest_algo_type: 0
05:47:42.368958 CON phy_init 0 [CTL.YAML] srs_chest_tol2_normalization_algo_type: 1
05:47:42.368958 CON phy_init 0 [CTL.YAML] srs_chest_tol2_constant_scaler: 32768
05:47:42.368959 CON phy_init 0 [CTL.YAML] bfw_power_normalization_alg_selector: 1
05:47:42.368959 CON phy_init 0 [CTL.YAML] bfw_beta_prescaler: 16384
05:47:42.368959 CON phy_init 0 [CTL.YAML] total_num_srs_chest_buffers: 3072
05:47:42.368959 CON phy_init 0 [CTL.YAML] send_static_bfw_wt_all_cplane: 1
05:47:42.368959 CON phy_init 0 [CTL.YAML] ul_pcap_capture_enable: 0
05:47:42.368960 CON phy_init 0 [CTL.YAML] ul_pcap_capture_thread_cpu_affinity: 0
05:47:42.368960 CON phy_init 0 [CTL.YAML] ul_pcap_capture_thread_sched_priority: 0
05:47:42.368960 CON phy_init 0 [CTL.YAML] pcap_logger_ul_cplane_enable: 0
05:47:42.368960 CON phy_init 0 [CTL.YAML] pcap_logger_dl_cplane_enable: 0
05:47:42.368960 CON phy_init 0 [CTL.YAML] pcap_logger_thread_cpu_affinity: 0
05:47:42.368961 CON phy_init 0 [CTL.YAML] pcap_logger_thread_sched_prio: 0
05:47:42.368961 CON phy_init 0 [CTL.YAML] pcap_logger_file_save_dir: .
05:47:42.368961 CON phy_init 0 [CTL.YAML] static_beam_id_start: 1
05:47:42.368961 CON phy_init 0 [CTL.YAML] static_beam_id_end: 16527
05:47:42.368962 CON phy_init 0 [CTL.YAML] dynamic_beam_id_start: 16528
05:47:42.368962 CON phy_init 0 [CTL.YAML] dynamic_beam_id_end: 32767
05:47:42.368962 CON phy_init 0 [CTL.YAML] ul_order_timeout_gpu_log_enable: 1
05:47:42.368962 CON phy_init 0 [CTL.YAML] pusch_workCancelMode: 2
05:47:42.368962 CON phy_init 0 [CTL.YAML] GPU-initiated comms DL: 1
05:47:42.368962 CON phy_init 0 [CTL.YAML] GPU-initiated comms (via CPU): 0
05:47:42.368962 CON phy_init 0 [CTL.YAML] CPU-initiated comms : 0
05:47:42.368963 CON phy_init 0 [CTL.YAML] Cell group: 1
05:47:42.368963 CON phy_init 0 [CTL.YAML] Cell group num: 1
05:47:42.368963 CON phy_init 0 [CTL.YAML] puxchPolarDcdrListSz: 8
05:47:42.368963 CON phy_init 0 [CTL.YAML] split_ul_cuda_streams: 0
05:47:42.368963 CON phy_init 0 [CTL.YAML] serialize_pucch_pusch: 0
05:47:42.368963 CON phy_init 0 [CTL.YAML] bfw_c_plane_chaining_mode: 1
05:47:42.368963 CON phy_init 0 [CTL.YAML] fh_stats_dump_cpu_core: -1
05:47:42.368964 CON phy_init 0 [CTL.YAML] fix_beta_dl: 0
05:47:42.368964 CON phy_init 0 [CTL.YAML] pdump_client_thread: -1
05:47:42.368964 CON phy_init 0 [CTL.YAML] profiler_sec: 0
05:47:42.368964 CON phy_init 0 [CTL.YAML] datalake_address: localhost
05:47:42.368964 CON phy_init 0 [CTL.YAML] dpdk_file_prefix: cuphycontroller
05:47:42.368964 CON phy_init 0 [CTL.YAML] puschrxChestFactorySettingsFilename:
05:47:42.368965 CON phy_init 0 [CTL.YAML] accu_tx_sched_disable: 0
05:47:42.368965 CON phy_init 0 [CTL.YAML] cplane_disable: 0
05:47:42.368965 CON phy_init 0 [CTL.YAML] disable_empw: 0
05:47:42.368965 CON phy_init 0 [CTL.YAML] dlc_alloc_cplane_bfw_txq: 0
05:47:42.368965 CON phy_init 0 [CTL.YAML] dlc_bfw_enable_divide_per_cell: 1
05:47:42.368966 CON phy_init 0 [CTL.YAML] dpdk_verbose_logs: 0
05:47:42.368966 CON phy_init 0 [CTL.YAML] enable_cpu_task_tracing: 1
05:47:42.368966 CON phy_init 0 [CTL.YAML] enable_dl_cqe_tracing: 0
05:47:42.368966 CON phy_init 0 [CTL.YAML] enable_l1_param_sanity_check: 0
05:47:42.368966 CON phy_init 0 [CTL.YAML] enable_ok_tb: 0
05:47:42.368966 CON phy_init 0 [CTL.YAML] enable_prepare_tracing: 1
05:47:42.368966 CON phy_init 0 [CTL.YAML] mCh_segment_proc_enable: 0
05:47:42.368967 CON phy_init 0 [CTL.YAML] pmu_metrics: 3
05:47:42.368967 CON phy_init 0 [CTL.YAML] puschCfo: 1
05:47:42.368967 CON phy_init 0 [CTL.YAML] puschDftSOfdm: 0
05:47:42.368967 CON phy_init 0 [CTL.YAML] puschEnablePerPrgChEst: 0
05:47:42.368967 CON phy_init 0 [CTL.YAML] puschRssi: 1
05:47:42.368967 CON phy_init 0 [CTL.YAML] puschSelectChEstAlgo: 1
05:47:42.368967 CON phy_init 0 [CTL.YAML] puschSelectEqCoeffAlgo: 3
05:47:42.368967 CON phy_init 0 [CTL.YAML] puschSinr: 2
05:47:42.368968 CON phy_init 0 [CTL.YAML] puschTbSizeCheck: 1
05:47:42.368968 CON phy_init 0 [CTL.YAML] puschTdi: 1
05:47:42.368968 CON phy_init 0 [CTL.YAML] puschTo: 1
05:47:42.368968 CON phy_init 0 [CTL.YAML] pusch_deviceGraphLaunchEn: 1
05:47:42.368968 CON phy_init 0 [CTL.YAML] ulc_alloc_cplane_bfw_txq: 1
05:47:42.368968 CON phy_init 0 [CTL.YAML] ulc_bfw_enable_divide_per_cell: 0
05:47:42.368968 CON phy_init 0 [CTL.YAML] ul_rx_pkt_tracing_level: 0
05:47:42.368969 CON phy_init 0 [CTL.YAML] ul_rx_pkt_tracing_level_srs: 0
05:47:42.368969 CON phy_init 0 [CTL.YAML] ul_warmup_frame_count: 8
05:47:42.368969 CON phy_init 0 [CTL.YAML] forcedNumCsi2Bits: 0
05:47:42.368969 CON phy_init 0 [CTL.YAML] pusch_waitTimeOutPostEarlyHarqUs: 3000
05:47:42.368969 CON phy_init 0 [CTL.YAML] pusch_waitTimeOutPreEarlyHarqUs: 3000
05:47:42.368969 CON phy_init 0 [CTL.YAML] validation: 0
05:47:42.368971 CON phy_init 0 [CTL.YAML] cqe_trace_slot_mask: 196800
05:47:42.368971 CON phy_init 0 [CTL.YAML] datalake_samples: 1000000
05:47:42.368971 CON phy_init 0 [CTL.YAML] num_ok_tb_slot: 0
05:47:42.368971 CON phy_init 0 [CTL.YAML] pusch_nMaxLdpcHetConfigs: 32
05:47:42.368971 CON phy_init 0 [CTL.YAML] sendCPlane_dlbfw_backoff_th_ns: 300000
05:47:42.368972 CON phy_init 0 [CTL.YAML] sendCPlane_ulbfw_backoff_th_ns: 300000
05:47:42.368972 CON phy_init 0 [CTL.YAML] ul_order_max_rx_pkts: 256
05:47:42.368972 CON phy_init 0 [CTL.YAML] ul_order_rx_pkts_timeout_ns: 50000
05:47:42.368972 CON phy_init 0 [CTL.YAML] ul_order_timeout_cpu_ns: 8000000
05:47:42.368972 CON phy_init 0 [CTL.YAML] ul_order_timeout_gpu_ns: 8000000
05:47:42.368972 CON phy_init 0 [CTL.YAML] ul_order_timeout_gpu_srs_ns: 5200000
05:47:42.368972 CON phy_init 0 [CTL.YAML] ul_order_timeout_log_interval_ns: 0
05:47:42.368973 CON phy_init 0 [CTL.YAML] ul_srs_aggr3_task_launch_offset_ns: 500000
05:47:42.368973 CON phy_init 0 [CTL.YAML] workers_sched_priority: 95
05:47:42.368973 CON phy_init 0 [CTL.YAML] cqe_trace_cell_mask: 1
05:47:42.368974 CON phy_init 0 [CTL.YAML] Number of Cell Configs: 1
05:47:42.368974 CON phy_init 0 [CTL.YAML] L2Adapter config file: /opt/nvidia/cuBB/cuPHY-CP/cuphycontroller/config/l2_adapter_config_F08_CG1.yaml
05:47:42.368974 CON phy_init 0 [CTL.YAML] Cell name: O-RU 0
05:47:42.368974 CON phy_init 0 [CTL.YAML] MU: 1
05:47:42.368975 CON phy_init 0 [CTL.YAML] ID: 1
05:47:42.368975 CON phy_init 0 [CTL.YAML] Number of MPlane Configs: 1
05:47:42.368975 CON phy_init 0 [CTL.YAML] Mplane ID: 1
05:47:42.368976 CON phy_init 0 [CTL.YAML] VLAN ID: 2
05:47:42.368976 CON phy_init 0 [CTL.YAML] Source Eth Address: b8:ce:f6:fe:62:f4
05:47:42.368977 CON phy_init 0 [CTL.YAML] Destination Eth Address: 20:04:9b:9e:27:a3
05:47:42.368978 CON phy_init 0 [CTL.YAML] NIC port: 0000:38:00.0
05:47:42.368978 CON phy_init 0 [CTL.YAML] RU Type: 3
05:47:42.368978 CON phy_init 0 [CTL.YAML] U-plane TXQs: 1
05:47:42.368978 CON phy_init 0 [CTL.YAML] DL compression method: 1
05:47:42.368978 CON phy_init 0 [CTL.YAML] DL iq bit width: 9
05:47:42.368978 CON phy_init 0 [CTL.YAML] UL compression method: 1
05:47:42.368979 CON phy_init 0 [CTL.YAML] UL iq bit width: 9
05:47:42.368979 CON phy_init 0 [CTL.YAML]
05:47:42.368979 CON phy_init 0 [CTL.YAML] Flow list SSB/PBCH:
05:47:42.368979 CON phy_init 0 [CTL.YAML] 32512
05:47:42.368980 CON phy_init 0 [CTL.YAML] 32513
05:47:42.368980 CON phy_init 0 [CTL.YAML] 32514
05:47:42.368980 CON phy_init 0 [CTL.YAML] 32515
05:47:42.368980 CON phy_init 0 [CTL.YAML] 32516
05:47:42.368980 CON phy_init 0 [CTL.YAML] 32517
05:47:42.368980 CON phy_init 0 [CTL.YAML] 32518
05:47:42.368980 CON phy_init 0 [CTL.YAML] 32519
05:47:42.368980 CON phy_init 0 [CTL.YAML] 32520
05:47:42.368981 CON phy_init 0 [CTL.YAML] 32521
05:47:42.368981 CON phy_init 0 [CTL.YAML] 32522
05:47:42.368981 CON phy_init 0 [CTL.YAML] 32523
05:47:42.368981 CON phy_init 0 [CTL.YAML] 32524
05:47:42.368981 CON phy_init 0 [CTL.YAML] 32525
05:47:42.368981 CON phy_init 0 [CTL.YAML] 32526
05:47:42.368981 CON phy_init 0 [CTL.YAML] 32527
05:47:42.368981 CON phy_init 0 [CTL.YAML] Flow list PDCCH:
05:47:42.368982 CON phy_init 0 [CTL.YAML] 32512
05:47:42.368982 CON phy_init 0 [CTL.YAML] 32513
05:47:42.368982 CON phy_init 0 [CTL.YAML] 32514
05:47:42.368982 CON phy_init 0 [CTL.YAML] 32515
05:47:42.368982 CON phy_init 0 [CTL.YAML] 32516
05:47:42.368982 CON phy_init 0 [CTL.YAML] 32517
05:47:42.368982 CON phy_init 0 [CTL.YAML] 32518
05:47:42.368982 CON phy_init 0 [CTL.YAML] 32519
05:47:42.368982 CON phy_init 0 [CTL.YAML] 32520
05:47:42.368983 CON phy_init 0 [CTL.YAML] 32521
05:47:42.368983 CON phy_init 0 [CTL.YAML] 32522
05:47:42.368983 CON phy_init 0 [CTL.YAML] 32523
05:47:42.368983 CON phy_init 0 [CTL.YAML] 32524
05:47:42.368983 CON phy_init 0 [CTL.YAML] 32525
05:47:42.368983 CON phy_init 0 [CTL.YAML] 32526
05:47:42.368983 CON phy_init 0 [CTL.YAML] 32527
05:47:42.368983 CON phy_init 0 [CTL.YAML] Flow list PDSCH:
05:47:42.368983 CON phy_init 0 [CTL.YAML] 32512
05:47:42.368984 CON phy_init 0 [CTL.YAML] 32513
05:47:42.368984 CON phy_init 0 [CTL.YAML] 32514
05:47:42.368984 CON phy_init 0 [CTL.YAML] 32515
05:47:42.368984 CON phy_init 0 [CTL.YAML] 32516
05:47:42.368984 CON phy_init 0 [CTL.YAML] 32517
05:47:42.368984 CON phy_init 0 [CTL.YAML] 32518
05:47:42.368984 CON phy_init 0 [CTL.YAML] 32519
05:47:42.368984 CON phy_init 0 [CTL.YAML] 32520
05:47:42.368984 CON phy_init 0 [CTL.YAML] 32521
05:47:42.368985 CON phy_init 0 [CTL.YAML] 32522
05:47:42.368985 CON phy_init 0 [CTL.YAML] 32523
05:47:42.368985 CON phy_init 0 [CTL.YAML] 32524
05:47:42.368985 CON phy_init 0 [CTL.YAML] 32525
05:47:42.368985 CON phy_init 0 [CTL.YAML] 32526
05:47:42.368985 CON phy_init 0 [CTL.YAML] 32527
05:47:42.368985 CON phy_init 0 [CTL.YAML] Flow list CSIRS:
05:47:42.368985 CON phy_init 0 [CTL.YAML] 32512
05:47:42.368986 CON phy_init 0 [CTL.YAML] 32513
05:47:42.368986 CON phy_init 0 [CTL.YAML] 32514
05:47:42.368986 CON phy_init 0 [CTL.YAML] 32515
05:47:42.368986 CON phy_init 0 [CTL.YAML] 32516
05:47:42.368986 CON phy_init 0 [CTL.YAML] 32517
05:47:42.368986 CON phy_init 0 [CTL.YAML] 32518
05:47:42.368986 CON phy_init 0 [CTL.YAML] 32519
05:47:42.368986 CON phy_init 0 [CTL.YAML] 32520
05:47:42.368986 CON phy_init 0 [CTL.YAML] 32521
05:47:42.368986 CON phy_init 0 [CTL.YAML] 32522
05:47:42.368987 CON phy_init 0 [CTL.YAML] 32523
05:47:42.368987 CON phy_init 0 [CTL.YAML] 32524
05:47:42.368987 CON phy_init 0 [CTL.YAML] 32525
05:47:42.368987 CON phy_init 0 [CTL.YAML] 32526
05:47:42.368987 CON phy_init 0 [CTL.YAML] 32527
05:47:42.368987 CON phy_init 0 [CTL.YAML] Flow list PUSCH:
05:47:42.368987 CON phy_init 0 [CTL.YAML] 32512
05:47:42.368987 CON phy_init 0 [CTL.YAML] 32513
05:47:42.368988 CON phy_init 0 [CTL.YAML] 32514
05:47:42.368988 CON phy_init 0 [CTL.YAML] 32515
05:47:42.368988 CON phy_init 0 [CTL.YAML] 32516
05:47:42.368988 CON phy_init 0 [CTL.YAML] 32517
05:47:42.368988 CON phy_init 0 [CTL.YAML] 32518
05:47:42.368988 CON phy_init 0 [CTL.YAML] 32519
05:47:42.368988 CON phy_init 0 [CTL.YAML] 32520
05:47:42.368988 CON phy_init 0 [CTL.YAML] 32521
05:47:42.368989 CON phy_init 0 [CTL.YAML] 32522
05:47:42.368989 CON phy_init 0 [CTL.YAML] 32523
05:47:42.368989 CON phy_init 0 [CTL.YAML] 32524
05:47:42.368989 CON phy_init 0 [CTL.YAML] 32525
05:47:42.368989 CON phy_init 0 [CTL.YAML] 32526
05:47:42.368989 CON phy_init 0 [CTL.YAML] 32527
05:47:42.368989 CON phy_init 0 [CTL.YAML] Flow list PUCCH:
05:47:42.368989 CON phy_init 0 [CTL.YAML] 32512
05:47:42.368990 CON phy_init 0 [CTL.YAML] 32513
05:47:42.368990 CON phy_init 0 [CTL.YAML] 32514
05:47:42.368990 CON phy_init 0 [CTL.YAML] 32515
05:47:42.368990 CON phy_init 0 [CTL.YAML] 32516
05:47:42.368990 CON phy_init 0 [CTL.YAML] 32517
05:47:42.368990 CON phy_init 0 [CTL.YAML] 32518
05:47:42.368990 CON phy_init 0 [CTL.YAML] 32519
05:47:42.368990 CON phy_init 0 [CTL.YAML] 32520
05:47:42.368990 CON phy_init 0 [CTL.YAML] 32521
05:47:42.368990 CON phy_init 0 [CTL.YAML] 32522
05:47:42.368991 CON phy_init 0 [CTL.YAML] 32523
05:47:42.368991 CON phy_init 0 [CTL.YAML] 32524
05:47:42.368991 CON phy_init 0 [CTL.YAML] 32525
05:47:42.368991 CON phy_init 0 [CTL.YAML] 32526
05:47:42.368991 CON phy_init 0 [CTL.YAML] 32527
05:47:42.368991 CON phy_init 0 [CTL.YAML] Flow list SRS:
05:47:42.368991 CON phy_init 0 [CTL.YAML] 32576
05:47:42.368991 CON phy_init 0 [CTL.YAML] 32577
05:47:42.368992 CON phy_init 0 [CTL.YAML] 32578
05:47:42.368992 CON phy_init 0 [CTL.YAML] 32579
05:47:42.368992 CON phy_init 0 [CTL.YAML] 32580
05:47:42.368992 CON phy_init 0 [CTL.YAML] 32581
05:47:42.368992 CON phy_init 0 [CTL.YAML] 32582
05:47:42.368992 CON phy_init 0 [CTL.YAML] 32583
05:47:42.368992 CON phy_init 0 [CTL.YAML] 32584
05:47:42.368992 CON phy_init 0 [CTL.YAML] 32585
05:47:42.368992 CON phy_init 0 [CTL.YAML] 32586
05:47:42.368992 CON phy_init 0 [CTL.YAML] 32587
05:47:42.368993 CON phy_init 0 [CTL.YAML] 32588
05:47:42.368993 CON phy_init 0 [CTL.YAML] 32589
05:47:42.368993 CON phy_init 0 [CTL.YAML] 32590
05:47:42.368993 CON phy_init 0 [CTL.YAML] 32591
05:47:42.368993 CON phy_init 0 [CTL.YAML] 32592
05:47:42.368993 CON phy_init 0 [CTL.YAML] 32593
05:47:42.368993 CON phy_init 0 [CTL.YAML] 32594
05:47:42.368993 CON phy_init 0 [CTL.YAML] 32595
05:47:42.368993 CON phy_init 0 [CTL.YAML] 32596
05:47:42.368993 CON phy_init 0 [CTL.YAML] 32597
05:47:42.368994 CON phy_init 0 [CTL.YAML] 32598
05:47:42.368994 CON phy_init 0 [CTL.YAML] 32599
05:47:42.368994 CON phy_init 0 [CTL.YAML] 32600
05:47:42.368994 CON phy_init 0 [CTL.YAML] 32601
05:47:42.368994 CON phy_init 0 [CTL.YAML] 32602
05:47:42.368994 CON phy_init 0 [CTL.YAML] 32603
05:47:42.368994 CON phy_init 0 [CTL.YAML] 32604
05:47:42.368994 CON phy_init 0 [CTL.YAML] 32605
05:47:42.368994 CON phy_init 0 [CTL.YAML] 32606
05:47:42.368994 CON phy_init 0 [CTL.YAML] 32607
05:47:42.368994 CON phy_init 0 [CTL.YAML] 32608
05:47:42.368995 CON phy_init 0 [CTL.YAML] 32609
05:47:42.368995 CON phy_init 0 [CTL.YAML] 32610
05:47:42.368995 CON phy_init 0 [CTL.YAML] 32611
05:47:42.368995 CON phy_init 0 [CTL.YAML] 32612
05:47:42.368995 CON phy_init 0 [CTL.YAML] 32613
05:47:42.368995 CON phy_init 0 [CTL.YAML] 32614
05:47:42.368995 CON phy_init 0 [CTL.YAML] 32615
05:47:42.368995 CON phy_init 0 [CTL.YAML] 32616
05:47:42.368995 CON phy_init 0 [CTL.YAML] 32617
05:47:42.368995 CON phy_init 0 [CTL.YAML] 32618
05:47:42.368996 CON phy_init 0 [CTL.YAML] 32619
05:47:42.368996 CON phy_init 0 [CTL.YAML] 32620
05:47:42.368996 CON phy_init 0 [CTL.YAML] 32621
05:47:42.368996 CON phy_init 0 [CTL.YAML] 32622
05:47:42.368996 CON phy_init 0 [CTL.YAML] 32623
05:47:42.368996 CON phy_init 0 [CTL.YAML] 32624
05:47:42.368996 CON phy_init 0 [CTL.YAML] 32625
05:47:42.368996 CON phy_init 0 [CTL.YAML] 32626
05:47:42.368996 CON phy_init 0 [CTL.YAML] 32627
05:47:42.368996 CON phy_init 0 [CTL.YAML] 32628
05:47:42.368997 CON phy_init 0 [CTL.YAML] 32629
05:47:42.368997 CON phy_init 0 [CTL.YAML] 32630
05:47:42.368997 CON phy_init 0 [CTL.YAML] 32631
05:47:42.368997 CON phy_init 0 [CTL.YAML] 32632
05:47:42.368997 CON phy_init 0 [CTL.YAML] 32633
05:47:42.368997 CON phy_init 0 [CTL.YAML] 32634
05:47:42.368997 CON phy_init 0 [CTL.YAML] 32635
05:47:42.368997 CON phy_init 0 [CTL.YAML] 32636
05:47:42.368997 CON phy_init 0 [CTL.YAML] 32637
05:47:42.368998 CON phy_init 0 [CTL.YAML] 32638
05:47:42.368998 CON phy_init 0 [CTL.YAML] 32639
05:47:42.368998 CON phy_init 0 [CTL.YAML] Flow list PRACH:
05:47:42.368998 CON phy_init 0 [CTL.YAML] 32544
05:47:42.368998 CON phy_init 0 [CTL.YAML] 32545
05:47:42.368998 CON phy_init 0 [CTL.YAML] 32546
05:47:42.368998 CON phy_init 0 [CTL.YAML] 32547
05:47:42.368998 CON phy_init 0 [CTL.YAML] 32548
05:47:42.368999 CON phy_init 0 [CTL.YAML] 32549
05:47:42.368999 CON phy_init 0 [CTL.YAML] 32550
05:47:42.368999 CON phy_init 0 [CTL.YAML] 32551
05:47:42.368999 CON phy_init 0 [CTL.YAML] 32552
05:47:42.368999 CON phy_init 0 [CTL.YAML] 32553
05:47:42.368999 CON phy_init 0 [CTL.YAML] 32554
05:47:42.368999 CON phy_init 0 [CTL.YAML] 32555
05:47:42.368999 CON phy_init 0 [CTL.YAML] 32556
05:47:42.368999 CON phy_init 0 [CTL.YAML] 32557
05:47:42.368999 CON phy_init 0 [CTL.YAML] 32558
05:47:42.369000 CON phy_init 0 [CTL.YAML] 32559
05:47:42.369000 CON phy_init 0 [CTL.YAML] PUSCH TV: /opt/nvidia/cuBB/testVectors/cuPhyChEstCoeffs.h5
05:47:42.369000 CON phy_init 0 [CTL.YAML] SRS TV: /opt/nvidia/cuBB/testVectors/cuPhyChEstCoeffs.h5
05:47:42.369000 CON phy_init 0 [CTL.YAML] Section_3 time offset: 58369
05:47:42.369000 CON phy_init 0 [CTL.YAML] nMaxRxAnt: 4
05:47:42.369000 CON phy_init 0 [CTL.YAML] PUSCH PRBs Stride: 273
05:47:42.369001 CON phy_init 0 [CTL.YAML] PRACH PRBs Stride: 12
05:47:42.369001 CON phy_init 0 [CTL.YAML] SRS PRBs Stride: 273
05:47:42.369001 CON phy_init 0 [CTL.YAML] PUSCH nMaxPrb: 136
05:47:42.369001 CON phy_init 0 [CTL.YAML] PUSCH nMaxRx: 4
05:47:42.369001 CON phy_init 0 [CTL.YAML] UL Gain Calibration: 48.68
05:47:42.369001 CON phy_init 0 [CTL.YAML] Lower guard bw: 845
05:47:42.369007 CON phy_init 0 [CTL.SCF] Updated CUDA_DEVICE_MAX_CONNECTIONS to 32 for green contexts
05:47:43.065831 CON phy_init 0 [CTL.SCF] Network interface for PCIe address 0000:38:00.0 : aerial00
05:47:43.065892 CON phy_init 0 [APP.UTILS] PHC clock: 1769665663.65887764
05:47:43.065925 CON phy_init 0 [APP.UTILS] CLOCK_TAI: 1769665663.65917523
05:47:43.065926 CON phy_init 0 [APP.UTILS] CLOCK_REALTIME: 1769665663.65917476
05:47:43.065927 CON phy_init 0 [APP.UTILS] TAI/REALTIME offset: 0 seconds
05:47:43.071549 WRN phy_init 0 [DRV.WORKER] Unable to set pmu_type=3 for non Grace system. Disabling pmu_metrics.
05:47:43.071561 WRN phy_init 0 [DRV.WORKER] Unable to set pmu_type=3 for non Grace system. Disabling pmu_metrics.
05:47:43.071562 WRN phy_init 0 [DRV.WORKER] Unable to set pmu_type=3 for non Grace system. Disabling pmu_metrics.
05:47:43.071565 WRN phy_init 0 [DRV.WORKER] Unable to set pmu_type=3 for non Grace system. Disabling pmu_metrics.
05:47:43.071565 WRN phy_init 0 [DRV.WORKER] Unable to set pmu_type=3 for non Grace system. Disabling pmu_metrics.
05:47:43.071565 WRN phy_init 0 [DRV.WORKER] Unable to set pmu_type=3 for non Grace system. Disabling pmu_metrics.
05:47:43.071566 WRN phy_init 0 [DRV.WORKER] Unable to set pmu_type=3 for non Grace system. Disabling pmu_metrics.
05:47:43.072993 CON phy_init 0 [DRV.CTX] CUDA_DEVICE_MAX_CONNECTIONS 32
05:47:43.072994 CON phy_init 0 [DRV.CTX] use_green_contexts 1
05:47:43.073007 CON phy_init 0 [DRV.CTX] Initial GPU resources retrieved via cuDeviceGetDevResource() have type 1 and SM count 58.
05:47:43.073402 CON phy_init 0 [DRV.CTX] PUSCH green context with SM count of 32.
05:47:43.073993 CON phy_init 0 [DRV.CTX] PUCCH green context with SM count of 8.
05:47:43.074264 CON phy_init 0 [DRV.CTX] PRACH green context with SM count of 10.
05:47:43.074546 CON phy_init 0 [DRV.CTX] PDSCH green context with SM count of 40.
05:47:43.074820 CON phy_init 0 [DRV.CTX] DL Ctrl green context with SM count of 8.
05:47:43.075368 CON phy_init 0 [DRV.CTX] UL order green context with SM count of 6.
05:47:43.075643 CON phy_init 0 [DRV.CTX] GPU comm green context with SM count of 16.
EAL: Detected CPU lcores: 64
EAL: Detected NUMA nodes: 2
EAL: Detected shared linkage of DPDK
EAL: Multi-process socket /var/run/dpdk/cuphycontroller/mp_socket
EAL: Selected IOVA mode 'PA'
EAL: 64 hugepages of size 2097152 reserved, but no mounted hugetlbfs found for that size
EAL: VFIO support initialized
EAL: Probe PCI driver: gpu_cuda (10de:27b8) device: 0000:27:00.0 (socket 0)
EAL: Probe PCI driver: mlx5_pci (15b3:101d) device: 0000:38:00.0 (socket 0)
05:47:43.342517 CON phy_init 0 [DRV.FH] Dynamic beam id start: 16528, end: 32767, num of beam ids per slots: 2192, number of consecutive slots with unique of beam ids: 7
05:47:44.004308 CON phy_init 0 [FH.DOCA] doca_gpu_dmabuf_fd returned 0 (DOCA_SUCCESS is 0)
05:47:44.004319 CON phy_init 0 [FH.DOCA] Mapping transmit queue buffer (0x7fd0be000000 size 4294967296B dmabuf fd 79) with dmabuf mode
PCAP_LOGGER Initialized
mlx5_common: Fail to create MR for address (0x7fe218000000)
mlx5_common: Device 0000:38:00.0 unable to DMA map
05:47:45.391021 ERR phy_init 0 [AERIAL_ORAN_FH_EVENT] [FH.LIB] Exception! Failed to DMA map addr 0x7fe218000000 for NIC 0000:38:00.0: Operation not permitted
05:47:45.391050 ERR phy_init 0 [AERIAL_ORAN_FH_EVENT] [DRV.FH] aerial_fh::register_memory error
05:47:45.391051 ERR phy_init 0 [AERIAL_CUPHYDRV_API_EVENT] [DRV.CTX] registerMem error
gRPC Server listening on 0.0.0.0:50051
05:47:45.600693 CON phy_init 0 [CTL.SCF] ====> PhyDriver initialized!
05:47:45.601195 CON phy_init 0 [NVIPC:YAML] nv_ipc_parse_yaml_node: PCAP msg_filter: enable all messages: 0x00-0xFF
05:47:45.601227 CON phy_init 0 [NVIPC:YAML] nv_ipc_parse_yaml_node: PCAP cell_filter: enable all cells 0-255
05:47:45.601640 CON phy_init 0 [NVIPC.DEBUG] nv_ipc_debug_open: prefix=nvipc fapi_type=1 nvipc_version=25.3.0 OK
05:47:45.651619 CON 17277 0 [NVIPC.DEBUG] pcap_shm_caching_thread_func: thread [nvipc_pcap_shm] started on CPU core [10] ...
05:47:45.680748 CON phy_init 0 [NVIPC.SHM] nvipc server initialized
05:47:45.680837 CON phy_init 0 [NVIPC.SHM] shm_ipc_open: forward_enable=0 fw_max_msg_buf_count=1365 fw_max_data_buf_count=341
05:47:45.680840 CON phy_init 0 [NVIPC.SHM] create_shm_nv_ipc_interface: OK. buf_size: cpu_msg=15000 cpu_data=576000 cpu_large=4096000
05:47:45.680852 CON phy_init 0 [L2A.TRANSPORT] phy_mac_transport[0] created. phy_cell_map.size=0 mac_cell_map.size=0 mapped=false cell_num=1
05:47:45.680858 CON phy_init 0 [L2A.TRANSPORT] init: loaded 1 nvipc instance, total_cell_num=1
05:47:45.680994 CON phy_init 0 [L2A.MODULE] PHY_module: transport_num=1 total_cell_num=1
05:47:45.712248 CON 17278 0 [NVIPC.EFD] [nvipc][core 00 ] share event_fd thread info: sched_policy=0 sched_priority=0
05:47:45.712292 CON 17278 0 [NVIPC.EFD] [nvipc] Listening for nvipc client to connect ...
05:47:46.605202 CON UlPhyDriver03 0 [DRV.WORKER] Thread UlPhyDriver03(worker_default) on CPU 3 initialized fmtlog
05:47:46.605245 CON UlPhyDriver02 0 [DRV.WORKER] Thread UlPhyDriver02(worker_default) on CPU 2 initialized fmtlog
05:47:46.605275 CON DlPhyDriver06 0 [DRV.WORKER] Thread DlPhyDriver06(worker_default) on CPU 6 initialized fmtlog
05:47:46.605286 CON DlPhyDriver07 0 [DRV.WORKER] Thread DlPhyDriver07(worker_default) on CPU 7 initialized fmtlog
05:47:46.605358 CON DlPhyDriver05 0 [DRV.WORKER] Thread DlPhyDriver05(worker_default) on CPU 5 initialized fmtlog
05:47:46.605389 CON DlPhyDriver04 0 [DRV.WORKER] Thread DlPhyDriver04(worker_default) on CPU 4 initialized fmtlog
05:47:46.605420 CON DebugWorker09 0 [DRV.WORKER] Thread DebugWorker09(worker_default) on CPU 9 initialized fmtlog
Lookup table populated with 13104 entries
05:47:49.654924 CON phy_main 0 [CTL.SCF] cuPHYController configured for 1 cells
05:47:49.654926 CON phy_main 0 [CTL.SCF] ====> cuPHYController initialized, L1 is ready!
05:47:49.654941 CON phy_main 0 [CTL.STARTUP_TIMES] {TI PERCENTAGE} <cuphycontroller main> Start Main:0.1,Parse Cuphycontroller YAML:0.0,Init nvlog:0.4,Cuda Set Device:5.8,Cuphy PTI Init:3.7,Init PHYDriver:34.6,Init cuphydriver:0.0,Make PHYDriverProxy:0.0,Init SCF FAPI:0.0,Create PHY_group:55.3,Start PHY_group:0.0, (total: 7325830.9us),
05:47:49.654947 CON phy_main 0 [CTL.STARTUP_TIMES] {TI DURATION} <cuphycontroller main> Start Main:6971.126,Parse Cuphycontroller YAML:2551.700,Init nvlog:30389.284,Cuda Set Device:427809.241,Cuphy PTI Init:269112.276,Init PHYDriver:2534766.365,Init cuphydriver:0.365,Make PHYDriverProxy:23.665,Init SCF FAPI:5.072,Create PHY_group:4053933.687,Start PHY_group:268.080,
05:47:49.654950 CON phy_main 0 [CTL.STARTUP_TIMES] {TI TIMESTAMPS} <cuphycontroller main> Start Main:1769665662329095886,Parse Cuphycontroller YAML:1769665662336067012,Init nvlog:1769665662338618712,Cuda Set Device:1769665662369007996,Cuphy PTI Init:1769665662796817237,Init PHYDriver:1769665663065929513,Init cuphydriver:1769665665600695878,Make PHYDriverProxy:1769665665600696243,Init SCF FAPI:1769665665600719908,Create PHY_group:1769665665600724980,Start PHY_group:1769665669654658667,End Main:1769665669654926747,
05:47:49.654972 CON 17280 0 [L2A.MODULE] cell_update_thread_func: OAM thread affinity set to cpu core 0
05:47:49.662663 CON msg_processing 0 [L2A.MODULE] Thread thread_func on CPU 8 initialized fmtlog
05:48:09.653290 CON 17278 0 [NVIPC.EFD] [nvipc] nvipc unix socket server connected
05:48:09.653324 CON 17278 0 [NVIPC.EFD] [nvipc] Received peer event_fd: 86
05:48:09.853397 CON 17278 0 [NVIPC.EFD] Share event_fd succeed: efd_tx=86, efd_rx=94
05:48:09.853398 CON 17278 0 [NVIPC.EFD] [nvipc] Listening for nvipc client to connect ...
05:48:10.685929 CON msg_processing 0 [SCF.PHY] on_config_request: CONFIG.req received for cell_id=0 numTLVs=69 state=0
05:48:10.686183 CON msg_processing 0 [SCF.PHY] update_phy_stat_configs_l1: PHY Cell Id = 41, M-Plane Id= 1
05:48:10.702046 CON msg_processing 0 [DRV.PUSCH] tvStatPrms: PUSCH enableDeviceGraphLaunch=1 enableCsiP2Fapiv3 = 1 nMaxLdpcHetConfigs = 32
05:48:10.702049 CON msg_processing 0 [DRV.PUSCH] Timeout values for wait kernels are 3000us and 3000us
05:48:10.702051 CON msg_processing 0 [DRV.PUSCH] static_params.nMaxPrb: 136
05:48:10.702051 CON msg_processing 0 [DRV.PUSCH] static_params.nMaxRx: 4
05:48:10.711661 CON msg_processing 0 [CUPHY.MEMFOOT] cuphyMemoryFootprint - GPU allocation: 49.593 MiB for cuPHY PUSCH channel object (0x2cc01440000).
05:48:10.711678 CON msg_processing 0 [CUPHY.PUSCH_RX] PuschRx: Running with eqCoeffAlgo 3
05:48:10.724417 CON msg_processing 0 [DRV.PUSCH] tvStatPrms: PUSCH enableDeviceGraphLaunch=1 enableCsiP2Fapiv3 = 1 nMaxLdpcHetConfigs = 32
05:48:10.724418 CON msg_processing 0 [DRV.PUSCH] Timeout values for wait kernels are 3000us and 3000us
05:48:10.724419 CON msg_processing 0 [DRV.PUSCH] static_params.nMaxPrb: 136
05:48:10.724419 CON msg_processing 0 [DRV.PUSCH] static_params.nMaxRx: 4
05:48:10.731137 CON msg_processing 0 [CUPHY.MEMFOOT] cuphyMemoryFootprint - GPU allocation: 49.593 MiB for cuPHY PUSCH channel object (0x2cc0144c000).
05:48:10.731142 CON msg_processing 0 [CUPHY.PUSCH_RX] PuschRx: Running with eqCoeffAlgo 3
05:48:10.743761 CON msg_processing 0 [DRV.PUSCH] tvStatPrms: PUSCH enableDeviceGraphLaunch=1 enableCsiP2Fapiv3 = 1 nMaxLdpcHetConfigs = 32
05:48:10.743762 CON msg_processing 0 [DRV.PUSCH] Timeout values for wait kernels are 3000us and 3000us
05:48:10.743762 CON msg_processing 0 [DRV.PUSCH] static_params.nMaxPrb: 136
05:48:10.743762 CON msg_processing 0 [DRV.PUSCH] static_params.nMaxRx: 4
05:48:10.750828 CON msg_processing 0 [CUPHY.MEMFOOT] cuphyMemoryFootprint - GPU allocation: 49.593 MiB for cuPHY PUSCH channel object (0x2cc01458000).
05:48:10.750833 CON msg_processing 0 [CUPHY.PUSCH_RX] PuschRx: Running with eqCoeffAlgo 3
05:48:10.763433 CON msg_processing 0 [DRV.PUSCH] tvStatPrms: PUSCH enableDeviceGraphLaunch=1 enableCsiP2Fapiv3 = 1 nMaxLdpcHetConfigs = 32
05:48:10.763433 CON msg_processing 0 [DRV.PUSCH] Timeout values for wait kernels are 3000us and 3000us
05:48:10.763434 CON msg_processing 0 [DRV.PUSCH] static_params.nMaxPrb: 136
05:48:10.763434 CON msg_processing 0 [DRV.PUSCH] static_params.nMaxRx: 4
05:48:10.769913 CON msg_processing 0 [CUPHY.MEMFOOT] cuphyMemoryFootprint - GPU allocation: 49.593 MiB for cuPHY PUSCH channel object (0x2cc01464000).
05:48:10.769918 CON msg_processing 0 [CUPHY.PUSCH_RX] PuschRx: Running with eqCoeffAlgo 3
05:48:10.770601 CON msg_processing 0 [CUPHY.MEMFOOT] cuphyMemoryFootprint - GPU allocation: 3.344 MiB for cuPHY PUCCH channel object (0x2cc01399a00).
05:48:10.771119 CON msg_processing 0 [CUPHY.MEMFOOT] cuphyMemoryFootprint - GPU allocation: 3.344 MiB for cuPHY PUCCH channel object (0x2cc0139a800).
05:48:10.771542 CON msg_processing 0 [CUPHY.MEMFOOT] cuphyMemoryFootprint - GPU allocation: 3.344 MiB for cuPHY PUCCH channel object (0x2cc0139b600).
05:48:10.771909 CON msg_processing 0 [CUPHY.MEMFOOT] cuphyMemoryFootprint - GPU allocation: 3.344 MiB for cuPHY PUCCH channel object (0x2cc0139c400).
05:48:10.772763 CON msg_processing 0 [CUPHY.MEMFOOT] cuphyMemoryFootprint - GPU allocation: 0.182 MiB for cuPHY PRACH channel object (0x2cc02b6a340).
05:48:10.773501 CON msg_processing 0 [CUPHY.MEMFOOT] cuphyMemoryFootprint - GPU allocation: 0.182 MiB for cuPHY PRACH channel object (0x2cc02b6a6c0).
05:48:10.776756 CON msg_processing 0 [CUPHY.MEMFOOT] cuphyMemoryFootprint - GPU allocation: 98.130 MiB for cuPHY PDSCH channel object (0x2cc02952400).
05:48:10.779776 CON msg_processing 0 [CUPHY.MEMFOOT] cuphyMemoryFootprint - GPU allocation: 98.130 MiB for cuPHY PDSCH channel object (0x2cc02953c00).
05:48:10.782786 CON msg_processing 0 [CUPHY.MEMFOOT] cuphyMemoryFootprint - GPU allocation: 98.130 MiB for cuPHY PDSCH channel object (0x2cc02955400).
05:48:10.785686 CON msg_processing 0 [CUPHY.MEMFOOT] cuphyMemoryFootprint - GPU allocation: 98.130 MiB for cuPHY PDSCH channel object (0x2cc02956c00).
05:48:10.788794 CON msg_processing 0 [CUPHY.MEMFOOT] cuphyMemoryFootprint - GPU allocation: 98.130 MiB for cuPHY PDSCH channel object (0x2cc02958400).
05:48:10.792174 CON msg_processing 0 [CUPHY.MEMFOOT] cuphyMemoryFootprint - GPU allocation: 98.130 MiB for cuPHY PDSCH channel object (0x2cc02959c00).
05:48:10.795376 CON msg_processing 0 [CUPHY.MEMFOOT] cuphyMemoryFootprint - GPU allocation: 98.130 MiB for cuPHY PDSCH channel object (0x2cc0295b400).
05:48:10.799154 CON msg_processing 0 [CUPHY.MEMFOOT] cuphyMemoryFootprint - GPU allocation: 98.130 MiB for cuPHY PDSCH channel object (0x2cc0295cc00).
05:48:10.802541 CON msg_processing 0 [CUPHY.MEMFOOT] cuphyMemoryFootprint - GPU allocation: 98.130 MiB for cuPHY PDSCH channel object (0x2cc0295e400).
05:48:10.805893 CON msg_processing 0 [CUPHY.MEMFOOT] cuphyMemoryFootprint - GPU allocation: 98.130 MiB for cuPHY PDSCH channel object (0x2cc08960000).
05:48:10.805982 CON msg_processing 0 [CUPHY.MEMFOOT] cuphyMemoryFootprint - GPU allocation: 0.001 MiB for cuPHY SSB channel object (0x2cc02bb3c00).
05:48:10.806023 CON msg_processing 0 [CUPHY.MEMFOOT] cuphyMemoryFootprint - GPU allocation: 0.001 MiB for cuPHY SSB channel object (0x2cc02bb5100).
05:48:10.806060 CON msg_processing 0 [CUPHY.MEMFOOT] cuphyMemoryFootprint - GPU allocation: 0.001 MiB for cuPHY SSB channel object (0x2cc02bb4d80).
05:48:10.806114 CON msg_processing 0 [CUPHY.MEMFOOT] cuphyMemoryFootprint - GPU allocation: 0.001 MiB for cuPHY SSB channel object (0x2cc02bb5480).
05:48:10.806155 CON msg_processing 0 [CUPHY.MEMFOOT] cuphyMemoryFootprint - GPU allocation: 0.001 MiB for cuPHY SSB channel object (0x2cc02bb5800).
05:48:10.806192 CON msg_processing 0 [CUPHY.MEMFOOT] cuphyMemoryFootprint - GPU allocation: 0.001 MiB for cuPHY SSB channel object (0x2cc02bb5b80).
05:48:10.806236 CON msg_processing 0 [CUPHY.MEMFOOT] cuphyMemoryFootprint - GPU allocation: 0.001 MiB for cuPHY SSB channel object (0x2cc02bb5f00).
05:48:10.806271 CON msg_processing 0 [CUPHY.MEMFOOT] cuphyMemoryFootprint - GPU allocation: 0.001 MiB for cuPHY SSB channel object (0x2cc02bb6280).
05:48:10.806308 CON msg_processing 0 [CUPHY.MEMFOOT] cuphyMemoryFootprint - GPU allocation: 0.001 MiB for cuPHY SSB channel object (0x2cc02bb6600).
05:48:10.806349 CON msg_processing 0 [CUPHY.MEMFOOT] cuphyMemoryFootprint - GPU allocation: 0.001 MiB for cuPHY SSB channel object (0x2cc02bb6980).
05:48:10.806425 CON msg_processing 0 [CUPHY.MEMFOOT] cuphyMemoryFootprint - GPU allocation: 1.607 MiB for cuPHY PDCCH channel object (0x2cc02d2c800).
05:48:10.806573 CON msg_processing 0 [CUPHY.MEMFOOT] cuphyMemoryFootprint - GPU allocation: 1.607 MiB for cuPHY PDCCH channel object (0x2cc02d2cd00).
05:48:10.806661 CON msg_processing 0 [CUPHY.MEMFOOT] cuphyMemoryFootprint - GPU allocation: 1.607 MiB for cuPHY PDCCH channel object (0x2cc02d2d200).
05:48:10.806782 CON msg_processing 0 [CUPHY.MEMFOOT] cuphyMemoryFootprint - GPU allocation: 1.607 MiB for cuPHY PDCCH channel object (0x2cc02d2d700).
05:48:10.806899 CON msg_processing 0 [CUPHY.MEMFOOT] cuphyMemoryFootprint - GPU allocation: 1.607 MiB for cuPHY PDCCH channel object (0x2cc02d2dc00).
05:48:10.807130 CON msg_processing 0 [CUPHY.MEMFOOT] cuphyMemoryFootprint - GPU allocation: 1.607 MiB for cuPHY PDCCH channel object (0x2cc02d2e100).
05:48:10.807245 CON msg_processing 0 [CUPHY.MEMFOOT] cuphyMemoryFootprint - GPU allocation: 1.607 MiB for cuPHY PDCCH channel object (0x2cc02d2e600).
05:48:10.807357 CON msg_processing 0 [CUPHY.MEMFOOT] cuphyMemoryFootprint - GPU allocation: 1.607 MiB for cuPHY PDCCH channel object (0x2cc02d2eb00).
05:48:10.807471 CON msg_processing 0 [CUPHY.MEMFOOT] cuphyMemoryFootprint - GPU allocation: 1.607 MiB for cuPHY PDCCH channel object (0x2cc02d2f000).
05:48:10.807616 CON msg_processing 0 [CUPHY.MEMFOOT] cuphyMemoryFootprint - GPU allocation: 1.607 MiB for cuPHY PDCCH channel object (0x2cc02d2f500).
05:48:10.807714 CON msg_processing 0 [CUPHY.MEMFOOT] cuphyMemoryFootprint - GPU allocation: 0.093 MiB for cuPHY CSIRS channel object (0x2cc0815e480).
05:48:10.807749 CON msg_processing 0 [CUPHY.MEMFOOT] cuphyMemoryFootprint - GPU allocation: 0.093 MiB for cuPHY CSIRS channel object (0x2cc0815e780).
05:48:10.807825 CON msg_processing 0 [CUPHY.MEMFOOT] cuphyMemoryFootprint - GPU allocation: 0.093 MiB for cuPHY CSIRS channel object (0x2cc0815ea80).
05:48:10.807857 CON msg_processing 0 [CUPHY.MEMFOOT] cuphyMemoryFootprint - GPU allocation: 0.093 MiB for cuPHY CSIRS channel object (0x2cc0815f080).
05:48:10.807888 CON msg_processing 0 [CUPHY.MEMFOOT] cuphyMemoryFootprint - GPU allocation: 0.093 MiB for cuPHY CSIRS channel object (0x2cc0815f380).
05:48:10.807918 CON msg_processing 0 [CUPHY.MEMFOOT] cuphyMemoryFootprint - GPU allocation: 0.093 MiB for cuPHY CSIRS channel object (0x2cc0815f680).
05:48:10.807945 CON msg_processing 0 [CUPHY.MEMFOOT] cuphyMemoryFootprint - GPU allocation: 0.093 MiB for cuPHY CSIRS channel object (0x2cc0815f980).
05:48:10.807988 CON msg_processing 0 [CUPHY.MEMFOOT] cuphyMemoryFootprint - GPU allocation: 0.093 MiB for cuPHY CSIRS channel object (0x2cc0815fc80).
05:48:10.808021 CON msg_processing 0 [CUPHY.MEMFOOT] cuphyMemoryFootprint - GPU allocation: 0.093 MiB for cuPHY CSIRS channel object (0x2cc08e80080).
05:48:10.808048 CON msg_processing 0 [CUPHY.MEMFOOT] cuphyMemoryFootprint - GPU allocation: 0.093 MiB for cuPHY CSIRS channel object (0x2cc08e80380).
05:48:10.808061 CON msg_processing 0 [DRV.API] Update cell: mplane_id=1 dl_grid_sz=273
05:48:10.808062 CON msg_processing 0 [DRV.API] Update cell: mplane_id=1 ul_grid_sz=273
05:48:10.808077 CON msg_processing 0 [SCF.PHY] on_config_request: create_cell_configs for cell_id=0 phy_cell_id=41 returned error_code=0
05:48:10.808093 CON msg_processing 0 [SCF.PHY] send_cell_config_response: Send CONFIG.response: cell_id=0 error_code=0x0
05:48:10.808128 CON msg_processing 0 [L2A.TRANSPORT] wrapper: configured_cells_mask=0x1 expected_mask=0x1 all_cells_configured=true - all cells configured
05:48:10.808156 CON msg_processing 0 [SCF.PHY] on_cell_start_request: Cell 0 Received START.request, sending START.response... phy_cell_id=41
05:48:10.808319 CON msg_processing 0 [L2A.TRANSPORT] wrapper: configured_cells_mask=0x1 expected_mask=0x1 all_cells_configured=true - all cells configured
05:48:10.816657 CON timer_thread 0 [L2A.TICK] Thread slot_indication_thread_sleep_method initialized fmtlog
05:48:10.816663 CON timer_thread 0 [L2A.TICK] PTP Configs: gps_alpha: 0 gps_beta: 0
05:48:10.816670 CON timer_thread 0 [L2A.TICK] Start time: tick=1769665690816659508, seconds since epoch = 1769665690, nanoseconds = 816659508
05:48:10.816672 CON timer_thread 0 [L2A.TICK] FIRST tick scheduled for: tick=1769665693240000000, seconds since epoch = 1769665693, nanoseconds = 240000000
05:48:13.240042 CON timer_thread 0 [SCF.PHY] Cell 0 | DL 0.00 Mbps 0 Slots | UL 0.00 Mbps 0 Slots CRC 0 ( 0) | Tick 0
05:48:13.245416 ERR UlPhyDriver03 0 [AERIAL_CUPHYDRV_API_EVENT] [DRV.FUNC_UL] ERROR: SFN 0.5 AGGR 3 task waiting for order kernel for more than 2000000 ns for Slot Map 1. Attempting PUSCH pipeline termination
05:48:13.246111 ERR msg_processing 0 [AERIAL_CUPHYDRV_API_EVENT] [DRV.API] SFN 0.15 No available UL input buffers st3 for cell 41
05:48:13.246118 WRN msg_processing 0 [SCF.PHY] send_phy_l1_enqueue_error_indication: L1 enqueue error SFN 0.15 cell_id=0
05:48:13.246120 ERR msg_processing 0 [AERIAL_NVIPC_API_EVENT] [SCF.PHY] Send Err.ind for SFN 0.15 cell_id=0 msg_id=0x81 err_code=0x33
05:48:13.246573 CON UlPhyDriver03 0 [DRV.FUNC_UL] SFN 0.5 AGGR 3 task PUSCH order kernel timeout waiting finished
05:48:13.246994 WRN UlPhyDriver02 0 [DRV.FH] sendCPlane_timingCheck : sendCPlane Timing error for ULC start_tx_time 1769665693246465000 current_time 1769665693246994292
05:48:13.246994 WRN UlPhyDriver02 0 [DRV.FH] sendCPlane_timingCheck: Error at oframe_id_ 0 osfid_ 7 oslotid_ 0
05:48:13.246994 ERR UlPhyDriver02 0 [AERIAL_CUPHYDRV_API_EVENT] [DRV.FUNC_UL] UL C-plane send error for cell index 0,error type 2 Map 2 Abort UL Tasks!
05:48:13.246996 ERR UlPhyDriver02 0 [AERIAL_CUPHYDRV_API_EVENT] [DRV.FUNC_UL] Calling ul_tx_error_fn 1491
05:48:13.246998 ERR UlPhyDriver02 0 [AERIAL_NVIPC_API_EVENT] [SCF.PHY] Send Err.ind for SFN 0.14 cell_id=0 msg_id=0x81 err_code=0x37
05:48:13.247006 ERR UlPhyDriver02 0 [AERIAL_CUPHYDRV_API_EVENT] [DRV.FUNC_UL] Task ul_aggr_1_cplane 0 aborted the tasklist for an error
05:48:13.247011 WRN UlPhyDriver02 0 [DRV.FUNC_UL] task_work_function_ul_aggr_1_orderKernel Task aborted for Slot Map 2
05:48:13.247012 WRN UlPhyDriver02 0 [DRV.FUNC_UL] task_work_function_ul_aggr_1_pucch_pusch Task aborted for Slot Map 2
05:48:13.247912 WRN UlPhyDriver03 0 [DRV.FUNC_UL] task_work_function_ul_aggr_3 Task aborted for Slot Map 2
05:48:13.248400 WRN UlPhyDriver02 0 [DRV.FUNC_UL] task_work_function_ul_aggr_3_early_uci_ind Task aborted for Slot Map 2
05:48:14.240009 CON timer_thread 0 [SCF.PHY] Cell 0 | DL 558.75 Mbps 1599 Slots | UL 79.35 Mbps 398 Slots CRC 1 ( 1) | Tick 2000
05:48:15.240009 CON timer_thread 0 [SCF.PHY] Cell 0 | DL 558.90 Mbps 1600 Slots | UL 79.91 Mbps 400 Slots CRC 0 ( 1) | Tick 4000
05:48:16.240009 CON timer_thread 0 [SCF.PHY] Cell 0 | DL 558.90 Mbps 1600 Slots | UL 79.91 Mbps 400 Slots CRC 0 ( 1) | Tick 6000
05:48:16.523673 ERR DebugWorker09 0 [AERIAL_CUPHYDRV_API_EVENT] [DRV.DLBUF] ERROR compression: DLBuffer Object Cell 41 waiting for compression start for more than 1500000 ns
05:48:16.523673 ERR DebugWorker09 0 [AERIAL_CUPHYDRV_API_EVENT] [DRV.FUNC_DL] Task DL 1 Map 129 got COMPRESSION DL wait start error
05:48:17.240008 CON timer_thread 0 [SCF.PHY] Cell 0 | DL 558.90 Mbps 1600 Slots | UL 79.91 Mbps 400 Slots CRC 0 ( 1) | Tick 8000
05:48:18.240009 CON timer_thread 0 [SCF.PHY] Cell 0 | DL 558.90 Mbps 1600 Slots | UL 79.91 Mbps 400 Slots CRC 0 ( 1) | Tick 10000
05:48:19.240008 CON timer_thread 0 [SCF.PHY] Cell 0 | DL 558.90 Mbps 1600 Slots | UL 79.74 Mbps 399 Slots CRC 0 ( 1) | Tick 12000
05:48:20.240009 CON timer_thread 0 [SCF.PHY] Cell 0 | DL 558.90 Mbps 1600 Slots | UL 80.07 Mbps 401 Slots CRC 0 ( 1) | Tick 14000
3839 Cell 0 Order kernel sem_idx_rx 2808 last_sem_idx_rx 2669 sem_idx_order 2808 last_sem_idx_order 2669 PUSCH PRBs 0/26688 PRACH PRBs 0/0. First packet received timeout after 4000000 ns F2S7S0 done = 0 current_time=1769665705428621312,last_timeout_log_time=0,total_rx_pkts=748
05:48:20.949915 ERR UlPhyDriver02 0 [AERIAL_CUPHYDRV_API_EVENT] [DRV.FUNC_UL] ERROR: SFN 770.14 AGGR 3 task waiting for order kernel for more than 2000000 ns for Slot Map 10. Attempting PUSCH pipeline termination
05:48:20.950412 ERR UlPhyDriver03 0 [AERIAL_CUPHYDRV_API_EVENT] [DRV.FUNC_UL] ERROR: SFN 770.15 AGGR 3 task waiting for order kernel for more than 2000000 ns for Slot Map 11. Attempting PUSCH pipeline termination
05:48:20.951106 ERR msg_processing 0 [AERIAL_CUPHYDRV_API_EVENT] [DRV.API] SFN 771.5 No available UL input buffers st3 for cell 41
05:48:20.951110 WRN msg_processing 0 [SCF.PHY] send_phy_l1_enqueue_error_indication: L1 enqueue error SFN 771.5 cell_id=0
05:48:20.951112 ERR msg_processing 0 [AERIAL_NVIPC_API_EVENT] [SCF.PHY] Send Err.ind for SFN 771.5 cell_id=0 msg_id=0x81 err_code=0x33
05:48:20.951349 ERR UlPhyDriver02 0 [AERIAL_CUPHY_API_EVENT] [DRV.FUNC_UL] SFN 770.14 Slot Map 10 Order kernel timeout error (exit condition 3) for cell index 0 Dyn index 0! Attempting PUSCH pipeline termination
05:48:20.951356 CON UlPhyDriver02 0 [DRV.FUNC_UL] SFN 770.14 AGGR 3 task PUSCH order kernel timeout waiting finished
05:48:20.951504 WRN UlPhyDriver02 0 [DRV.FH] sendCPlane_timingCheck : sendCPlane Timing error for ULC start_tx_time 1769665700951465000 current_time 1769665700951504723
05:48:20.951505 WRN UlPhyDriver02 0 [DRV.FH] sendCPlane_timingCheck: Error at oframe_id_ 3 osfid_ 2 oslotid_ 0
05:48:20.951505 ERR UlPhyDriver02 0 [AERIAL_CUPHYDRV_API_EVENT] [DRV.FUNC_UL] UL C-plane send error for cell index 0,error type 2 Map 12 Abort UL Tasks!
05:48:20.951506 ERR UlPhyDriver02 0 [AERIAL_CUPHYDRV_API_EVENT] [DRV.FUNC_UL] Calling ul_tx_error_fn 1491
05:48:20.951508 ERR UlPhyDriver02 0 [AERIAL_NVIPC_API_EVENT] [SCF.PHY] Send Err.ind for SFN 771.4 cell_id=0 msg_id=0x81 err_code=0x37
05:48:20.951512 ERR UlPhyDriver02 0 [AERIAL_CUPHYDRV_API_EVENT] [DRV.FUNC_UL] Task ul_aggr_1_cplane 0 aborted the tasklist for an error
05:48:20.951516 WRN UlPhyDriver02 0 [DRV.FUNC_UL] task_work_function_ul_aggr_1_orderKernel Task aborted for Slot Map 12
05:48:20.951517 WRN UlPhyDriver02 0 [DRV.FUNC_UL] task_work_function_ul_aggr_1_pucch_pusch Task aborted for Slot Map 12
05:48:20.952416 CON UlPhyDriver03 0 [DRV.FUNC_UL] SFN 770.15 AGGR 3 task PUSCH order kernel timeout waiting finished
05:48:20.952912 WRN UlPhyDriver03 0 [DRV.FUNC_UL] task_work_function_ul_aggr_3 Task aborted for Slot Map 12
05:48:20.953403 WRN UlPhyDriver02 0 [DRV.FUNC_UL] task_work_function_ul_aggr_3_early_uci_ind Task aborted for Slot Map 12
05:48:21.240008 CON timer_thread 0 [SCF.PHY] Cell 0 | DL 558.90 Mbps 1600 Slots | UL 79.11 Mbps 398 Slots CRC 2 ( 3) | Tick 16000
05:48:22.240009 CON timer_thread 0 [SCF.PHY] Cell 0 | DL 558.90 Mbps 1600 Slots | UL 79.91 Mbps 400 Slots CRC 0 ( 3) | Tick 18000
05:48:23.240008 CON timer_thread 0 [SCF.PHY] Cell 0 | DL 558.90 Mbps 1600 Slots | UL 79.91 Mbps 400 Slots CRC 0 ( 3) | Tick 20000
05:48:24.240009 CON timer_thread 0 [SCF.PHY] Cell 0 | DL 558.90 Mbps 1600 Slots | UL 79.91 Mbps 400 Slots CRC 0 ( 3) | Tick 22000
05:48:25.240008 CON timer_thread 0 [SCF.PHY] Cell 0 | DL 558.90 Mbps 1600 Slots | UL 79.91 Mbps 400 Slots CRC 0 ( 3) | Tick 24000
05:48:26.240008 CON timer_thread 0 [SCF.PHY] Cell 0 | DL 558.90 Mbps 1600 Slots | UL 79.91 Mbps 400 Slots CRC 0 ( 3) | Tick 26000
05:48:27.240008 CON timer_thread 0 [SCF.PHY] Cell 0 | DL 558.90 Mbps 1600 Slots | UL 79.91 Mbps 400 Slots CRC 0 ( 3) | Tick 28000
05:48:28.240009 CON timer_thread 0 [SCF.PHY] Cell 0 | DL 558.90 Mbps 1600 Slots | UL 79.91 Mbps 400 Slots CRC 0 ( 3) | Tick 30000
05:48:28.284694 CON msg_processing 0 [L2A.TICK] TTI Generator refcount = 0, stopping timer thread.
05:48:28.284986 CON msg_processing 0 [L2A.TICK] TTI Generator refcount = 0, stopped timer thread
^C05:48:34.535112 CON phy_main 0 [CTL.SCF] Signal 2 received, preparing to exit...
PhyDriverCtx destructor starting
flushing counters completed
05:48:34.635199 CON phy_main 0 [DRV.CTX] PhyDriverCtx destructor starting
05:48:34.635205 CON phy_main 0 [DRV.UL_PACKET_SUMMARY] slot,cell_0_early,cell_0_ontime,cell_0_late,
05:48:34.635206 CON phy_main 0 [DRV.UL_PACKET_SUMMARY] Slot 4 | 0,46527,61473 |
05:48:34.635207 CON phy_main 0 [DRV.UL_PACKET_SUMMARY] Slot 5 | 0,38888,141112 |
05:48:34.635207 CON phy_main 0 [DRV.UL_PACKET_SUMMARY] Slot 14 | 0,44392,63320 |
05:48:34.635208 CON phy_main 0 [DRV.UL_PACKET_SUMMARY] Slot 15 | 0,38846,140674 |
05:48:34.635208 CON phy_main 0 [DRV.UL_PACKET_SUMMARY] Slot 24 | 0,45321,62391 |
05:48:34.635208 CON phy_main 0 [DRV.UL_PACKET_SUMMARY] Slot 25 | 0,38587,140933 |
05:48:34.635209 CON phy_main 0 [DRV.UL_PACKET_SUMMARY] Slot 34 | 0,44916,62796 |
05:48:34.635209 CON phy_main 0 [DRV.UL_PACKET_SUMMARY] Slot 35 | 0,39425,140095 |
05:48:34.635209 CON phy_main 0 [DRV.UL_PACKET_SUMMARY] Slot 44 | 0,45643,62069 |
05:48:34.635210 CON phy_main 0 [DRV.UL_PACKET_SUMMARY] Slot 45 | 0,38577,140943 |
05:48:34.635210 CON phy_main 0 [DRV.UL_PACKET_SUMMARY] Slot 54 | 0,44650,63042 |
05:48:34.635210 CON phy_main 0 [DRV.UL_PACKET_SUMMARY] Slot 55 | 0,39132,140388 |
05:48:34.635210 CON phy_main 0 [DRV.UL_PACKET_SUMMARY] Slot 64 | 0,46042,61382 |
05:48:34.635211 CON phy_main 0 [DRV.UL_PACKET_SUMMARY] Slot 65 | 0,38141,140899 |
05:48:34.635211 CON phy_main 0 [DRV.UL_PACKET_SUMMARY] Slot 74 | 0,44343,63369 |
05:48:34.635211 CON phy_main 0 [DRV.UL_PACKET_SUMMARY] Slot 75 | 0,39129,140391 |
05:48:34.635220 CON phy_main 0 [DRV.UL_PACKET_SUMMARY] Slot 4 | 0.00,43.08,56.92 |
05:48:34.635221 CON phy_main 0 [DRV.UL_PACKET_SUMMARY] Slot 5 | 0.00,21.60,78.40 |
05:48:34.635222 CON phy_main 0 [DRV.UL_PACKET_SUMMARY] Slot 14 | 0.00,41.21,58.79 |
05:48:34.635223 CON phy_main 0 [DRV.UL_PACKET_SUMMARY] Slot 15 | 0.00,21.64,78.36 |
05:48:34.635224 CON phy_main 0 [DRV.UL_PACKET_SUMMARY] Slot 24 | 0.00,42.08,57.92 |
05:48:34.635224 CON phy_main 0 [DRV.UL_PACKET_SUMMARY] Slot 25 | 0.00,21.49,78.51 |
05:48:34.635225 CON phy_main 0 [DRV.UL_PACKET_SUMMARY] Slot 34 | 0.00,41.70,58.30 |
05:48:34.635226 CON phy_main 0 [DRV.UL_PACKET_SUMMARY] Slot 35 | 0.00,21.96,78.04 |
05:48:34.635227 CON phy_main 0 [DRV.UL_PACKET_SUMMARY] Slot 44 | 0.00,42.38,57.62 |
05:48:34.635227 CON phy_main 0 [DRV.UL_PACKET_SUMMARY] Slot 45 | 0.00,21.49,78.51 |
05:48:34.635228 CON phy_main 0 [DRV.UL_PACKET_SUMMARY] Slot 54 | 0.00,41.46,58.54 |
05:48:34.635229 CON phy_main 0 [DRV.UL_PACKET_SUMMARY] Slot 55 | 0.00,21.80,78.20 |
05:48:34.635230 CON phy_main 0 [DRV.UL_PACKET_SUMMARY] Slot 64 | 0.00,42.86,57.14 |
05:48:34.635230 CON phy_main 0 [DRV.UL_PACKET_SUMMARY] Slot 65 | 0.00,21.30,78.70 |
05:48:34.635231 CON phy_main 0 [DRV.UL_PACKET_SUMMARY] Slot 74 | 0.00,41.17,58.83 |
05:48:34.635232 CON phy_main 0 [DRV.UL_PACKET_SUMMARY] Slot 75 | 0.00,21.80,78.20 |
05:48:34.635413 CON phy_main 0 [DRV.CTX] flushing counters completed
05:48:36.835613 CON phy_main 0 [FH.NIC] NIC 0000:38:00.0 stats:
05:48:36.835618 CON phy_main 0 [FH.NIC] tx_packets: 1460668
05:48:36.835621 CON phy_main 0 [FH.NIC] rx_packets: 0
05:48:36.835622 CON phy_main 0 [FH.NIC] tx_bytes: 723118784
05:48:36.835623 CON phy_main 0 [FH.NIC] rx_bytes: 0
05:48:36.835623 CON phy_main 0 [FH.NIC] tx_errors: 0
05:48:36.835624 CON phy_main 0 [FH.NIC] rx_errors: 0
05:48:36.835625 CON phy_main 0 [FH.NIC] rx_missed: 0
05:48:36.835625 CON phy_main 0 [FH.NIC] rx_nombuf: 0
PhyDriverCtx destructor completed successfully
05:48:37.463603 CON phy_main 0 [DRV.CTX] Total CPU regular memory 81023728 B / 79124 KiB / 77 MiB
05:48:37.463605 CON phy_main 0 [DRV.CTX] Total CPU pinned memory 179525068 B / 175317 KiB / 171 MiB
05:48:37.463605 CON phy_main 0 [DRV.CTX] Total GPU regular memory 2960551744 B / 2891163 KiB / 2823 MiB
05:48:37.463605 CON phy_main 0 [DRV.CTX] Total GPU pinned memory 77755584 B / 75933 KiB / 74 MiB
05:48:37.463617 CON phy_main 0 [DRV.CTX] PhyDriverCtx destructor completed successfully
05:48:37.463759 CON phy_main 0 [CTL.SCF] ====> PhyDriver finalized! Exit from signal_handler after 1s delay...
EXIT successfully at: /opt/nvidia/cuBB/cuPHY-CP/cuphycontroller/examples/cuphycontroller_scf.cpp line 73
Now I have two problems:
- Will the error “mlx5_common: Fail to create MR for address (0x7ee1d4000000)” affect the Simulator E2E test?
- What‘s the meaning of the setting “gpu_init_comms_via_cpu: 1” and “gpu_init_comms_via_cpu: 0”?
