I have a custom Orin NX (16GB) carrier card with only a few overlays provided by the board manufacturer. I want to repurpose 2 Jetson I/O pins that are currently UART (uart2_tx_px4 and uart_rx_px5) to GPIO inputs. I also want to repurpose 1 Jetson I/O pin that is currently GPIO input (soc_gpio39_p…

I found the problem with this particular pin. In the design guide, https://developer.nvidia.com/downloads/jetson-orin-nx-series-nano-series-design-guide : [image] therefore PX.04 / GP32_UART2_TXD / UART0_TXD should not be used as GPIO (cannot be used as input due to output-only buffer, probably c…

*** Please note that this reply is generated by LLM automatically *** To incorporate the changes you’ve made to the pinmux configuration into the Device Tree Binary (DTB) used at boot time, you’ll need to follow these steps: Create a custom Device Tree Source (DTS) file: You’ve already modified t…

Hi flybyya23, [image] flybyya23: I have the full DTSI file if needed, but I didn’t see the equivalent file in the source tree to replace): gpio.dtsi (added to gpio@2200000…gpio_main_default…gpio-input): The configuration in pinmux and gpio dtsi are loaded in early boot stage(i.e. MB1) rathe…

[image] KevinFFF: Is this pinmux spreadsheet provided by your vendor? If not, please request them for this as the board is developed by them. They do not provide a pinmux spreadsheet, but I generated an unmodified pinmux/gpio DTSI file from NVIDIAs spreadsheet and the files here in the buil…

Hello @flybyya23 , Hope everything is going great! Allow me to jump into the conversation. I believe tegra234-mb1-bct-gpio-p3767-hdmi-a03.dtsi should be “imported” by the tegra234-mb1-bct-pinmux-p3767-hdmi-a03.dtsi. You can open the pinmux dtsi and check the first lines, and there should be an i…

Thanks @proventusnova and @KevinFFF . Update. I was able to confirm that include @proventusnova thanks. I haven’t tried devmem yet, but I was able to use the changes in the 1st post and use PN.01 as a PWM. I was also able to use PX.05 (uart2_rx_px5) as an input, though technically it was already …

Additional update. I tried the busybox devmem process but was unable to read the register address the address I computed for PX.04: base address 0x2430000 (PADCTL_A0 for GP3) port offset 0x114 (webpage) pin offset 4 (PX.04) therefore I believe the appropriate address for PX.04 is 0x02430118 $ …

Update 3! I found this method to check configuration: cat /sys/kernel/debug/pinctrl/2430000.pinmux/pinconf-groups | grep px4 -A 14 88 (uart2_tx_px4): pull=0 tristate=0 enable-input=1 open-drain=0 io-reset=0 rcv-sel=0 io-hv=0 schmitt=…

[image] flybyya23: therefore I believe the appropriate address for PX.04 is 0x02430118 The pinmux register for PX.04(UART2_TX) is 0x0243d050. Please run the following command instead. $ sudo busybox devmem 0x0243d050 [image] flybyya23: I noticed that “function” is still uartb for both …

[image] KevinFFF: The pinmux register for PX.04(UART2_TX) is 0x0243d050. Please run the following command instead. $ sudo busybox devmem 0x0243d050 @KevinFFF Thanks. I think I see how you got to that address so I’ll document for myself, though I have a question along the way. I am using th…

[image] flybyya23: Do you know the gpio control register addresses for reading/writing for these pins? Maybe you can also refer to the following thread for the address for both PADCTRL and DRA. Calculating/Getting register adresses of gpio pins - #10 by KevinFFF [image] flybyya23: $ sud…

Modify Pinmux/GPIO functions - custom Jetson Orin NX carrier

Robotics & Edge Computing Jetson Systems Jetson Orin NX

KevinFFF November 28, 2025, 1:50am 24

Hi @flybyya23,

We have updated the pinmux spreadsheet for Orin NX/Nano to v1.1, which includes this fix.

Thanks for reporting the issue.

Uart b rts and cts as gpio mode in jetson orin nx

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Modify Pinmux/GPIO functions - custom Jetson Orin NX carrier

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