Hello all
we have a product which will not need a power button.
What is a bare minimal design approach for this?
Looking at the timing diagram there is no need for delays on setting EN high
Can POWER_EN just be tied to the VDD_IN supply and then use the SYS_RESET output signal to enable the carrier board supplies?
This would eliminate a lot of complexity and reduce build cost.
can anybody comment?
Hi, the POWER_EN should be high after VDD_IN is stable. The timing is about ~80ms. You can refer to the Power ON/OFF Logic design of P3449 schematic as below for auto-power-on design.
are you simply using the 412k and 2.2uF to create a very slow RC combination, (with time constant 0.9seconds) ?
I wont have a reset or power button on the product, so can i omit these?
The RC is also necessary for auto-power-on to let VDD_IN in stable first and then pull power_en high.
hi Trumany
yes I understansd that part…
I dont need a reset or power button, so can i completely eliminate this part?
And just tie the left side of the 412k resistor to VDD_IN ?
It should be ok in theory, but has not been validated yet.
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