In TRM, page no: 2934, it is mentioned as
THS_SETTLE: Settle time for data lane when moving from LP to HS (LP11->LP01->LP00), this setting determines how
many LP clock cycles (204 MHz lp clock cycles) to wait, after LP00, before starting to look at the data. 85ns + 6 * UI < (Ths-
settle-programmed + 6) * lp clock periods < 145ns + 10 * UI
Our data rate is 1 Gbps, so Mipi Clock is 500 MHz. Our Mipi CSI-2 Tx device requires HS_SETTLE value is 145ns.
As per the register NVCSI_PHY_0_NVCSI_CIL_A_CONTROL_0, the LP clock freq: 204MHz, so the time = 4.9ns.
Register value: THS_SETTLE = Mipi CSI-2 Tx HS-SETTLE / 4.9ns
= 145ns / 4.9ns
As per TRM,
85ns + 6 * UI < (Ths-settle-programmed + 6) * lp clock periods < 145ns + 10 * UI
85ns + 6 * 2ns < (30 + 6) * 4.9ns < 145ns + 10 * 2ns
97ns < 176.4 ns < 165ns
The computed value does not meet the condition in registers. How to proceed further??