Nvidia jetson carrier board spi config

HI i have enabled the spi1 and sp3 using jetsion-io.py and ebale to do spi loop test on spi0.0 0.1 1.0 1.1 successfully .but when i try to connect the bmi270 spi based sensor and load the driver for read chip id with /* SPI1, 40pin header, Pin 19(MOSI), Pin 21(MISO), Pin 23(CLK), Pin 24(CS) */
spi@3210000 {
status = “okay”;
pinctrl-names = “default”;
//pinctrl-0 = <&jetson_io_pinmux>;
// pinctrl-names = “default”;
//pinctrl-0 = <&spi1_sck_pin &spi1_miso_pin &spi1_mosi_pin &spi1_cs0_pin>;
bmi270@0 {
compatible = “bosch,bmi270”;
reg = <0x0>;
spi-max-frequency = <5000000>;
interrupt-parent = <&gpio>;
interrupts = <97 IRQ_TYPE_EDGE_RISING>; // Using pin 97
spi-cpha;
spi-cpol;

    controller-data {
        nvidia,enable-hw-based-cs;
        nvidia,rx-clk-tap-delay = <0x10>;
        nvidia,tx-clk-tap-delay = <0x0>;
    };
};

bmi270@1 {
    compatible = "bosch,bmi270";
    reg = <0x1>;
    spi-max-frequency = <5000000>;
    interrupt-parent = <&gpio>;
    interrupts = <97 IRQ_TYPE_EDGE_RISING>;

    controller-data {
        nvidia,enable-hw-based-cs;
        nvidia,rx-clk-tap-delay = <0x10>;
        nvidia,tx-clk-tap-delay = <0x0>;
    };
};

};
tis driver is getting loaded ,but unable to see any signals in cs miso mosi of 40 oin connector and chip read fails can some one help me on this ,i an doing this on jetson orin nx

Hi kathir1,

Are you using the devkit or custom board for Orin NX?
What’s the Jetpack version in use?

Please share the full dmesg for further check.

Have you used the scope to check if the signal output is correct?

custom board . 36.4 latest jetson package

to verify my board is working
i have used PZ.07 as gpio which is sudo gpioset gpiochip0 137=0 137=1 its is not toggled while this time PZ.07 is not claimed as spi1

Have you used the scope to check if the signal output is correct? i did not get anything

dmesg: i am dynamically instering bmi270.ko

spidev 0.0 BMI270 SPI probe started
spidev 0.0unexpected chipid 0x00 thiis is i am getting

[ 17.867858] r8168: enP8p1s0: link up
[ 17.867953] IPv6: ADDRCONF(NETDEV_CHANGE): enP8p1s0: link becomes ready
[ 53.765498] bmi270 spi0.0: BMI270 SPI probe started
[ 53.765521] bmi270 spi0.0: Failed to get CS GPIO
[ 53.766592] bmi270 spi0.0: BMI270 Chip ID: 0x00
[ 53.766598] bmi270 spi0.0: Unexpected chip ID: 0x00
[ 53.766644] bmi270 spi0.1: BMI270 SPI probe started
[ 53.766659] bmi270 spi0.1: Failed to get CS GPIO
[ 53.767515] bmi270 spi0.1: BMI270 Chip ID: 0x00
[ 53.767518] bmi270 spi0.1: Unexpected chip ID: 0x00
[ 53.767553] bmi270 spi1.0: BMI270 SPI probe started
[ 53.767562] bmi270 spi1.0: Failed to get CS GPIO
[ 53.768508] bmi270 spi1.0: BMI270 Chip ID: 0x00
[ 53.768511] bmi270 spi1.0: Unexpected chip ID: 0x00
[ 53.768529] bmi270 spi1.1: BMI270 SPI probe started
[ 53.768534] bmi270 spi1.1: Failed to get CS GPIO
[ 53.768876] bmi270 spi1.1: BMI270 Chip ID: 0x00
[ 53.768878] bmi270 spi1.1: Unexpected chip ID: 0x00

do we need to bind the 40 pin connector to the soc pins or bmi270@0 {
compatible = “bosch,bmi270”;
reg = <0x0>;
spi-max-frequency = <5000000>;
interrupt-parent = <&gpio>;
interrupts = <97 IRQ_TYPE_EDGE_RISING>; // Using pin 97
spi-cpha;
spi-cpol;

    controller-data {
        nvidia,enable-hw-based-cs;
        nvidia,rx-clk-tap-delay = <0x10>;
        nvidia,tx-clk-tap-delay = <0x0>;
    };
};

bmi270@1 {
    compatible = "bosch,bmi270";
    reg = <0x1>;
    spi-max-frequency = <5000000>;
    interrupt-parent = <&gpio>;
    interrupts = <97 IRQ_TYPE_EDGE_RISING>;

    controller-data {
        nvidia,enable-hw-based-cs;
        nvidia,rx-clk-tap-delay = <0x10>;
        nvidia,tx-clk-tap-delay = <0x0>;
    };
};
``` in this we are setting status =okay this itself fine ??

pin 122 (SPI3_SCK_PY0): 2430000.pinmux (GPIO UNCLAIMED) (HOG) function rsvd3 group spi3_sck_py0
pin 123 (SPI3_MISO_PY1): 2430000.pinmux (GPIO UNCLAIMED) (HOG) function rsvd3 group spi3_miso_py1
pin 124 (SPI3_MOSI_PY2): 2430000.pinmux (GPIO UNCLAIMED) (HOG) function rsvd3 group spi3_mosi_py2
pin 125 (SPI3_CS0_PY3): 2430000.pinmux (GPIO UNCLAIMED) (HOG) function rsvd3 group spi3_cs0_py3
pin 126 (SPI3_CS1_PY4): 2430000.pinmux (GPIO UNCLAIMED) (HOG) function rsvd3 group spi3_cs1_py4
pin 127 (UART5_TX_PY5): (MUX UNCLAIMED) (GPIO UNCLAIMED)
pin 128 (UART5_RX_PY6): (MUX UNCLAIMED) (GPIO UNCLAIMED)
pin 129 (UART5_RTS_PY7): (MUX UNCLAIMED) (GPIO UNCLAIMED)
pin 130 (UART5_CTS_PZ0): (MUX UNCLAIMED) (GPIO UNCLAIMED)
pin 131 (USB_VBUS_EN0_PZ1): (MUX UNCLAIMED) (GPIO UNCLAIMED)
pin 132 (USB_VBUS_EN1_PZ2): (MUX UNCLAIMED) (GPIO UNCLAIMED)
pin 133 (SPI1_SCK_PZ3): 2430000.pinmux (GPIO UNCLAIMED) (HOG) function rsvd3 group spi1_sck_pz3
pin 134 (SPI1_MISO_PZ4): 2430000.pinmux (GPIO UNCLAIMED) (HOG) function rsvd3 group spi1_miso_pz4
pin 135 (SPI1_MOSI_PZ5): 2430000.pinmux (GPIO UNCLAIMED) (HOG) function rsvd3 group spi1_mosi_pz5
pin 136 (SPI1_CS0_PZ6): 2430000.pinmux (GPIO UNCLAIMED) (HOG) function rsvd3 group spi1_cs0_pz6
pin 137 (SPI1_CS1_PZ7): 2430000.pinmux (GPIO UNCLAIMED) (HOG) function rsvd3 group spi1_cs1_pz7
here in 40 pin connector it is claimed but in gpioinfo soc pins remain unused

@KevinFFF do you have any idea on this

For the custom carrier board, I would suggest you using the pinmux spreadsheet to configure the pins for SPI.
If you have the similar design as the devkit, Jetson-IO may also work on your board as you’ve verified SPI loopback test.

It seems the CS not working as exepected.
Are you using SPI0_CS1 for BMI270 module?

Please share the block diagram of your connections with us to know your setup.

I would also like the check the full dmesg and device tree.
Please share them as file here.

hi ,

i have solved the problem in spi mode 0 and three it is working on spi@0 and spi@1 with 40 pin header dtbo