PCIe GEN3 PEX_CLK frequency

Hi,

On PCIe controllor C0 (or pcie@14180000), we have GEN3 NVMe SSD.
In device-tree, nvidia,max-speed is set to 3 for pcie@14180000.
lspci -vvv shows:

LnkCap:	Port #0, Speed 8GT/s, Width x8
LnkSta:	Speed 8GT/s, Width x2

I want to know the frequency of PEX_CLK0_N/P in this GEN3 case.

From the software, I can see:

cat /sys/kernel/debug/clk/pex0_core_0/clk_rate 
250000000
cat clk_summary | grep pex
 pex1_core_5                                                1            1   250000000   250000000          0 0  
 pex0_core_4                                                0            0   500000000   500000000          0 0  
 pex0_core_3                                                1            1    62500000    62500000          0 0  
 pex0_core_1                                                1            1    62500000    62500000          0 0  
 pex0_core_0                                                1            1   250000000   250000000          0 0  

So, it looks like the frequency of PEX_CLK0_N/P is 250 MHz?
However, according to the links below, it seems PCIe GEN3 clock frequency is 8 GHz:

I am a bit confused. In my GEN3 case, is PEX_CLK0_N/P 250 MHhz or 8 GHz? Why pex0_core_0 clock shows 250 MHz which is way lower then PCIe GEN3 standard?
Or pex0_core_0 clock is an internal reference clock, then PLL on SoC/SoM will generate 8 GHz clock on PEX_CLK0_N/P?

Thanks.

Sorry for the late response, is this still an issue to support? Thanks

Yes, still an issue. please help.

Yes, pex0_core_0 is internal clock.
PEX_CLK0_N/P is reference clock, which is 100 MHz per PCIe spec.
What are referring to(8GHz at Gen3) is PCIe lane serial frequency. When serializing the data and routing it via PHY layer, desired clk rate is generated by PLL based on PCIe Gen speed.

PCIe endpoint has to source 100 MHz clock from root port via PEX_CLK0_N/P pins and generate desired PCIe lane serial frequency based on Gen speed.

Thanks,
Manikanta