Pin conflicts between AGX Orin Design Guide and DevKit

Dear NVidia Team

We came across conflicts between pin description in the Design Guide of the AGX Orin (Jetson_AGX_Orin_Pin_Descriptions.nvxlsx) and the Schematic of the Developer Kit. Pins that are mentioned as reserved are connected to signals:

  • UART7 at B48/B49
  • 3.3V to L53
  • J62 to GND

In the Guide it mentions that “RSVD - must be left unconnected unless otherwise directed”. Can you elaborate? Should we follow the design guide or the developer kit schematic?
Thank you.

Best regards

Hi, please refer to below settings:

Pin B48/B49 are rsvd.
Pin L53 is supplied by 3.3V.
Pin J62 is shorted to GND as ‘TEMP_SHDN_EN_N’.

Hi Trumany

Thank you for the fast reply, this clarifies it.
One other question, PCIe x4 (C4) hast the following lanes:

When we look at the DevKits M.2 Key M connector, the order of the Lanes is from bottom to top, meaning

TX/RX11 is lane 0
TX/RX10 is lane 1
TX/RX23 is lane 2
TX/RX22 is lane 3

Is this correct?
How is the order for PCIe x8 (C5) ?

It is correct as it support lane swap for better routing. You can use or not use that by your routing design.

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