Jetson AGX Xavier PCIE Controller C4

I am designing a custom carrier PCBA for the AGX Xavier module. It appears that there is a discrepancy between the OEM design guide and the technical reference manual regarding the PCIE lane count of PCIE controller C4. Table 22 of the OEM design guide shows that PCIE controller C4 can only support a 2-lane PCIE interface. Figure 9.17 in the technical reference manual shows PCIE controller C4 as being capable of a 4-lane PCIE interface. I have some questions about this.

  1. Which document is correct?

  2. Is the PCIE controller C4 capable of a 4-lane PCIE interface?

  3. What is the UPHY lane mapping for PCIE controller C4?

Hi, TRM is chip level manual. Some characters are not validated on Jetson platform, so please follow OEM DG to make design.