R32 SPE Uart output


My carrier board needs to use UART2 on B16 & B15. I see that it’s currently being used to output SPE info:

SPE VERSION #: R00.01.19 Created: Sep 19 2018 @ 11:02:47
HW Function test
Start Scheduler.
in late init

welcome to lk
adc initialized
chip_revision initialized
starting app shell
entering main console loop

How might I disable this & free the serial port up for my application?

Hi hannaBarbera,

Are you sure you are using uart2?? The OEM DG indicates UART2 for our carrier board is for M.2 key E slot.

I’m sure I’m using pins B16 & B15? :S

Hello, hannaBarbera:
The log you pasted should come from UART4 (D8,D5) in default SDK setting of Jetson TX2 carrier board.
UART2 (B16,B15,A16,A15) is not used for any debug purpose.

please confirm.


Perhaps I’m confused yes, I’m also using D8 & D5. Question remains, how do I disable SPE uart output?

What is the exact UART you want to use?

For the SPE log, you could try the method in this thread.

Uarts: D8/D5, D9/D10, B16/B15 & G12/H12

Hello, hannaBarbera:
D8/D5 is UARTG, which is used by both BPMP firmware and SPE firmware for message output as you’ve seen. It’s not recommended using that port for other purpose.
D9/D10 (UARTC) and B16/B15 (UARTB) are free and you can use them.
G12/H12 (UARTA) is the main debug port. Please don’t use it for other purpose.


Hello hannaBabera,

How could you get above output? I cant get like this output. Which pins you are using?
my developer board in link. could you say which pins in j17 or j21?


Im using https://developer.nvidia.com/embedded/dlc/l4t_rt_aux_cpu_src demo

Hello, hamzaygrtc:
Please take a look at https://devtalk.nvidia.com/default/topic/1062575/freertos-spe-fw-help-for-pin-control-/
there’s some detailed description for UART and GPIO.


Hi hannaBarbera,

I use J17 serial port to see if the gpio sample code run with nothing printed out while uart sample code can get message “Message from SPE R5 UART”.

The GPIO.md mentions " Make sure that the kernel/bootloader is not accessing these GPIOs (Usually, this can be done by modifying the device tree file) and no external module is connected to the Jetson expansion header ". How can I confirm whether the kernel/bootloader can access these GPIOs or not?

Hello, garretzou:
To run GPIO app, please follow steps in “doc/gpio.md”.
Since SPE and CCPLEX are running simultaneously, if they are accessing/configuring same module, like GPIOs, that module may not function as desired.
You can debug that issue by checking the DTS and find whether configuration like pinmux conflicts with desired configuration.

Also, you can check register value directly in Linux side and if that’s different from SPE firmware setting, it must be updated by somewhere.


Dear jachen,


Yes, I did several times following the step in “doc/gpio.md”, the step four says:
Short GPIO pins of the 30 pin header J26 pin 17 and pin 15, this should print
out “GPIO input irq triggered” message since pin 17 is configured as OUT which
drives the pin 15 which is configured as INPUT and also has interrupt enabled.
It do not mention through which serial port can I get that message, UARTC(J17) or UARTG(J10)?

“doc/uart.md” says Use a wire to connect UARTC TX and Rx (in Jetson TX2 carrier board, they
are pin 5 and 4 in J17), then the following message will output from
SPE firmware debug UART port, i.e. UARTG:
Message from SPE R5 UART
But I get the message in UARTC(J17) without connecting pin 5 and 4 in J17.

That makes me confused about at which serial port the “GPIO input irq triggered” message is printed out?

Hello, garretzou:
Generally, there are 2 UART ports, one is SPE debug port, which will output messages in SPE firmware, called by printf, etc. Another is a UART port for external use, and SPE firmware can communicate with external devices like GPS, or whatever device through UART.
So all messages mentioned in doc which is printed by SPE firmware should output to SPE debug port.

UART test app will do 2 things:

  1. UART port under test will output that message. ‘Message from SPE R5 UART’
  2. UART port under test will also accept input message and print to SPE debug port.

So to debug SPE firmware first, please connect SPE debug port first. In TX2, as doc says: ‘UARTG is also used by SPE firmware debug message output in Jetson TX2.’

Hope that can clear your confusion.


Dear jachen,

Your reply helps me a lot.

So both serial port and SPE debug port can get the “GPIO input irq triggered” message in “doc/gpio.md”?

Hello, garretzou:
no. If you enabled GPIO app, only SPE debug UART port can output ‘GPIO input irq triggered’.


Got it. Thank you.

I am using tx2 dev kit. The SPE debug UART port is in J10, cause too many pins on it make it difficult to fly the UART port. So how to get a debug module of J10?