RGMII Delay Skew Between Clock and Data

I’m going to use KSZ9131 for gigabit Etyernet, and would like to clarify do I understand correctly skew requirements

  1. length RGMII_TX_Data and RGMII_TX_CTRL should be equal with RGMII_Tx_Clk length.
  2. RGMII_Rx_Clk length should be greater RGMII_Rx_Data and RGMII_Rx_CTRL than 1.5ns and less than 2.0ns.
    Do I understand correctly?

PHY which I use, by default add 2 ns delay to the RXC output pin with respect to RX_CTL and RXD[3:0] output pins.
PHY does not add any delay locally at its TXC, TX_CTL and TXD[3:0] input pins.
So, i need enable internal delay in PHY. How to do this, in what file? In DTS file, or in driver?

Hi, please refer to the chapter Gigabit Ethernet in Orin Design Guide for your custom design. There is no other request than that. For the PHY setting, you may need to check with vendor first.

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