I’m going to use KSZ9131 for gigabit Etyernet, and would like to clarify do I understand correctly skew requirements
- length RGMII_TX_Data and RGMII_TX_CTRL should be equal with RGMII_Tx_Clk length.
- RGMII_Rx_Clk length should be greater RGMII_Rx_Data and RGMII_Rx_CTRL than 1.5ns and less than 2.0ns.
Do I understand correctly?
PHY which I use, by default add 2 ns delay to the RXC output pin with respect to RX_CTL and RXD[3:0] output pins.
PHY does not add any delay locally at its TXC, TX_CTL and TXD[3:0] input pins.
So, i need enable internal delay in PHY. How to do this, in what file? In DTS file, or in driver?