S-parameters and ibis models of Xavier module and chip

Autonomous Machines Jetson & Embedded Systems Jetson AGX Xavier
1

Hi,

I want to perform signal integrity simulations to my carrier board, inclusing the Xavier module.
I downloaded Jetson_AGX_Xavier_Sparameters_IBIS_Models.zip which seems very helpful, but I didn’t find any text file or PDF that describes the models and how to connect them. where can I find this doc?
currently I’m especially intersted in the PCIe interface and I guess i need to use the UPHY models.
there are 2 models under this directory - one of them is the board and one the package? how each port related to specific TX or RX signal?
a document that describes the connectivity is necessary.
Thank you,
Tohar

2

Hi, we are checking it internally, will update once available.

3

Hi,

Any update?
This is urgent…
the pins that are most important to me are:
NVHS0_TX[0:3]_N/P
NVHS0_SLVS_RX[0:3]_N/P

Thanks

4

Sorry, internal checking is still ongoing.

5

tohar

When I went through this I just worked with the SI engineer and we made our best guess, also due to lack of support basically.

Frustrating, I know. But I shared a similar experience.

6

Hi tohar,

We are still checking with corresponding team about your question. Before result coming out, if you are designing custom carrier board, then there is no need to be blocked by this, because the OEM DG can cover it. There are some routing guidelines in OEM DG, if you follow that well, there should be no signal quality issue on high speed IO.

7

Hi Any update on this one?

1 Like
9

Not yet. Is there anything on that block your custom design?

10

The latest package was release in DLC, please check that first.

http://developer.nvidia.com/embedded/dlc/jetson-agx-xavier-sparameter-files