SPE access to main GPIOs

Autonomous Machines Jetson & Embedded Systems Jetson Xavier NX
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1

Hello,

I noticed from this thread that we were not allowed to access main GPIOs from SPE:

Is that still valid, or the feature is now available (Xavier NX platform)?

Many thanks

Andrea

3

Hello, Andrea:
Sure. Basically, SPE in Xavier (including Xavier AGX and Xavier NX) is within AON domain, and the modules accessed by SPE, like GPIOs, UARTs, SPIs, etc., should be limited in AON domain, officially.

br
ChenJian

4

Thanks for the confirmation Jachen.

If I register AON chip, as in GPIO example, it works fine as expected:

gpio_chip_register(0, &tegra_gpio_ops_aon, &tegra_gpio_id_aon)

Then I tried the same, with MAIN chip structures:

gpio_chip_register(1, &tegra_gpio_ops_main, &tegra_gpio_id_main)

But then getting this from system shell:

[  337.895826] nvgpu: 17000000.gv11b gv11b_fb_print_fault_info:710  [ERR] [MMU FAULT] mmu engine id:  4, ch id:  -1, fault addr: 0x519000, fault addr aperture: 0, fault type: invalid pde, access type: virt write, 
[  337.896875] nvgpu: 17000000.gv11b gv11b_fb_print_fault_info:719  [ERR] [MMU FAULT] protected mode: 0, client type: hub, client id:  host, gpc id if client type is gpc: 0,

So I was wondering: given that all main GPIO structures are already there, is there a less “official” way to unlock this capability?

Thanks again

Andrea

5

Hello, Andrea:
Sorry that feature (access non-AON modules from SPE firmware) is not supported due to several reasons. So we cannot support that.
Please do not touch modules out of AON cluster in SPE firmware.

br
ChenJian

br
ChenJian

6

Ok I understand, thanks for your kind support

Andrea

8

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