SPE GTE example application for GPIO transitions

Hello, I am trying Sensor Processing Engine GTE example application described here:
https://docs.nvidia.com/jetson/spe/md__home_dipenp_rel-32-new_rt-aux-cpu-demo_delete_gmc4_32_85_public_l4t-rt_rt-aux-cpu-demo_doc_gte-app.html
As far as I understood, tegra_gte_slice_set_enable_mask in spe/gte-app.c configures GTE to timestamp both GPIO_APP_IN IRQs and level transitions, but in the end I am unluckily only getting TTY logs for NV_AON_GTE_SLICE1_IRQ_GPIO, not for NV_AON_GTE_SLICE2_IRQ_GPIO_2 events.
Another symptom, possibly related to the same issue, is that if I execute gpio-app example, can_gpio_irq_handler is properly called, but if at the same time I monitor GPIO_APP_IN level by gpio_get_value, I always get zero for this input. So, also in this case: GPIO IRQ works fine, but no input level changes can be probed.
Going back to GTE, I would like to simply timestamp input level transitions, without having to enable GPIO interrupts, but from what said above I am not able to detect the relative events.

Many thanks in advance

Andrea

Hello, andrea:

  1. For GPIO GTE timestamp, you should enable GPIO app as well. And once GPIO IN get level changing, you should see the log and timestamp recorded.
  2. You can check the code. After GPIO IN and OUT shorted, GPIO IN just shows level of GPIO OUT. And gpio_set_value(GPIO_APP_OUT, 0); is always called in ISR. I’m not sure where you put the ‘gpio_get_value’. You can add some print in ISR, before GPIO OUT is set to 0.

br
ChenJian

Hello Jachen, thanks for the hint, I can confirm that also GPIO app is enabled by default when ENABLE_GTE_APP=1 in rt-aux-cpu-demo/soc/t19x/target_specific.mk .
I also confirm to have tested GPIO app by using the suggested setup, with GPIO IN and OUT shorted. GPIO IRQ is correctly triggered, but gpio_get_value print in ISR always says zero. Same thing for GTE app: IRQ event is detected and timestamped, but no GPIO_APP_IN transition event is generated.
When running GPIO/GTE app, I can correctly observe GPIO_APP_IN level changing in Linux by gpiod lib, so we can be sure that hardware feedback is properly setup. GPIO input looks for some reason not routed to the SPE layer, as confirmed by gpio_get_value, although it can still generate IRQs

Hello, Andrea:
Can you try to comment out the code gpio_set_value(GPIO_APP_OUT, 0); at “l4t-rt/rt-aux-cpu-demo/app/gpio-app.c” and print out gpio_get_value again?

Also, you can share your code if possible.

br
ChenJian

Hi Jachen, sorry, I found a bug in my code, now I can properly log transitions at GPIO_APP_IN by gpio_get_value.
Here an excerpt, where GPIO_IN is the printf added to monitor GPIO_APP_IN level:

gpio_app_task - Settingcan_gpio_irq_handler - gpio irq triggered - setting GPIO_APP_OUT to 0 
Slice Id: 1, Event Id: 5 (GPIO IRQ), Edge = falling, Time stamp = 139f18ca2
Slice Id: 1, Event Id: 5 (GPIO IRQ), Edge = rising, Time stamp = 139f18d18
 GPIO_APP_OUT to 1 - IRQ should trigger
GPIO_IN 1
GPIO_IN 0

Now all working fine, except for GPIO_APP_IN transition events mapped to GTE slice 2 which never happen.
I am using exactly the original SPE example code, just added following line to gpio_app_task:

    *(uint32_t*)0x0c302040 = 0x75;

This is needed because GPIO_APP_IN is configured as I2C SDA in my device tree, so I have to override relative pinmux to set it to GPIO as required in GPIO app

Hello Jachen, could you possibly confirm that NV_AON_GTE_SLICE2_IRQ_GPIO_2 events at GTE slice 2 (signal transitions for GPIO_APP_IN) are also expected to happen in GTE demo app? As showed above, I can only see logs for NV_AON_GTE_SLICE1_IRQ_GPIO at slice 1.
Thanks, Andrea

Hello, andrea.pascolini:
Sorry for delayed response.
Theoretically, both slices should be triggered.

        tegra_gte_slice_set_enable_mask(&tegra_gte_id_aon,
                                        1, /* slice number 1 */
                                        BIT(NV_AON_GTE_SLICE1_IRQ_GPIO));

Slice 1 should be triggered when GPIO IRQ happens.

    tegra_gte_slice_set_enable_mask(&tegra_gte_id_aon,
                                    2, /* slice number 2 */
                                    BIT(NV_AON_GTE_SLICE2_IRQ_GPIO_2));

Slice 2 should be triggered when GPIO_IN interrupt happens.

Anyway, from your test, it seems that you do not get slice 2, correct?
Please help to confirm that GPIO_IN is configured as TEGRA_AON_GPIO_ID(BB, 1), and that’s exactly the pin connected.
NV_AON_GTE_SLICE2_IRQ_GPIO_2 should be the correct setting for GPIO BB1, if you still cannot get the correct log.
I may need more time to test. (sorry that I cannot physically access

br
ChenJian`

Hello jachen, thanks for the update.

I confirm I am not getting events for NV_AON_GTE_SLICE2_IRQ_GPIO_2 assigned to slice 2.
About GPIO_IN (GPIO_APP_IN in code), this is my gpio-aon.h:

#if defined(ENABLE_SPE_FOR_NX)
#define GPIO_APP_OUT TEGRA_AON_GPIO_ID(CC, 4) /* GPIO_CC 4, pin 15, J12 */
#define GPIO_APP_IN  TEGRA_AON_GPIO_ID(DD, 0) /* GPIO_DD 0, pin 27, J12 */                                                                                            
#else
#define GPIO_APP_OUT TEGRA_AON_GPIO_ID(BB, 0) /* GPIO_BB 0, pin 16, J30 */
#define GPIO_APP_IN  TEGRA_AON_GPIO_ID(BB, 1) /* GPIO_BB 1, pin 32, J30 */
#endif

I am using Xavier NX, so have ENABLE_SPE_FOR_NX set to 1 in makefile, thererefore GPIO_APP_IN is mapped to (DD, 0), not to (BB, 1)

Andrea

Hello, andrea.pascolini:
With GPIO DD0, you can try to change the slice2 bit.
Replace
NV_AON_GTE_SLICE2_IRQ_GPIO_2
with
NV_AON_GTE_SLICE2_IRQ_GPIO_14

Let me know if you have any progress.

br
ChenJian

Hi Jachen, I confirm that reassigning the slice 2 bit solves my issue: now I can properly detect GPIO_APP_IN transitions, even with disabled GPIO IRQs.

Many thanks for you kind support

Andrea

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