SPI connection direction on Jetson Nano

Hi All,

can anyone please let me know why is the direction of the pins highlighted in attached image into the Nano. I think generally the chip select, MOSI, Clock should be going out from the Nano module to the slave devices ?

Is there any specific reason to draw it as in the below image ?

thanks

image

There is “Basic SPI Master and Slave Connections” under that showing the directions.

I think , The basic diagram should shows things as they are , MOSI should be coming out of Nano if Nano is the master.

The direction is different when nano is master or slave as listed in “Basic SPI Master and Slave Connections”.

In either case all the direction cannot be as input.

Those are all bi-direction in figure 10-2, and that’s why to add figure 10-3 to illustrate.

In the Orcad schematic as show below the CS is input but MOSI is output which is not matching the schematic in figure 10-3

image.png

Thanks for the finding, they should be all bi-direction as showed on level shift side.

Hi All, can I get the layout design of Jetson Nano carrier board for reference ?

It is in the package: https://developer.nvidia.com/jetson-nano-carrier-board-design-files