SPI CS control!?

Hi,

I’m using SPIDEV and I’m having a problem…

I have a device which requires the following sequence:

CS_LOW
Send 5 bytes
CS_HIGH

Here’s my code:

void MemWrite16(unsigned long ftAddress, unsigned int ftData16)
{
dataBuffer[0] = (char) ((ftAddress >> 16) | MEM_WRITE);
dataBuffer[1] = (char) (ftAddress >> 8);
dataBuffer[2] = (char) (ftAddress);
dataBuffer[3] = (char) (ftData16);
dataBuffer[4] = (char) (ftData16 >> 8);
xfer_spi.len = 5;
xfer_spi.cs_change = 0;
xfer_spi.bits_per_word = 8;
ioctl(file_spi, SPI_IOC_MESSAGE(1), &xfer_spi);
}

My problem is that CS get’s pulsed in between each byte - I have tried setting cs_change to 1 and 5 but nothing seems to change the behavior.

Can you advice how I can achieve the desired outcome?

Thanks
Lasse

Could you print the cs_inactive_cycles and inactive_cycles in the spi driver in …/kernel/kernel-4.4/drivers/spi/spi-tegra114.c