I’m working with an SPI to UART chip connected to my Jetson TX1 devboard.
My chip working using chipselect-gpio, but I see a lot of wasted time. 5us between CS activating and SCLK starting, 12us between SCLK stopping and CS deactivating, and about 12us between data bytes when sending multiple bytes. I have all controller-data values set to 0x00. Because of this inefficiency I want to try switching to enable-hw-based-cs to reduce some of the waiting. I set it up in the device tree, and I do see the CS toggling with less latency, though still about 5us sometimes, other times 0us. I tested spidev and using the hardware chip select, it has almost zero wasted time between CS active, no latency between data bytes, and no delay between between data and CS inactive.
My problem is: when I perform a read from my driver immediately followed by a write the system does not disable the CS between the two packets so my uart chip does not process the write packet. In some cases it seems as though the CS never is disabled after a read.
The driver for my SPI-uart chip uses regmap to read/write to the SPI and I have not been able to trace the exact call stack through the regmap.c to the spi-tegra114.c to diagnose why the CS line is not deactivating between read and write. This behavior does not exist with SW based CS, even when cs-inactive-cycles is 0.
Questions: Could this be a regmap issue? I could convert my driver to use direct SPI calls. Is this CS behavior something that can be controlled via the tegra spi registers? Why does spidev behave differently?
Any input you can provide is very welcome.