Spidev of Jetson nano-emmc core board cannot be used

[ShaneCCC]

Just find below link for the r32.3.1 for reference. For r32.4.3 may need time to check.

Check pinmux on spi0&1 on jetson-nano

Thanks ysp123ysp I attached the u-boot.bin here for someone need to enable SPI function. Rename it to u-boot.bin and replace the …/Linux_for_tegra/bootloader/t210ref/p3450-porg/u-boot.bin and reflash the device. u-boot.bin.txt (469.8 KB)

[ShaneCCC]

For r32.4.3 emmc version:

1. Apply the kernel patch for GPIO to build the Image and replace it.

commit 7035ec4c1c3de0535f8491c1ca96814325bd8fc4
Author: snchen <snchen@nvidia.com>
Date:   Fri Sep 6 15:56:47 2019 +0800

    gpio: tegra: fix failed to set the to SFIO

    Can't set the GPIO pin to SFIO by device tree.

    bug 200549751

    Change-Id: Idd331a594cb82b3a5ea4fc47c2784490ff99629f
    Signed-off-by: snchen <snchen@nvidia.com>

diff --git a/drivers/gpio/gpio-tegra.c b/drivers/gpio/gpio-tegra.c
index e101044..09dd6e4 100644
--- a/drivers/gpio/gpio-tegra.c
+++ b/drivers/gpio/gpio-tegra.c
@@ -217,6 +217,11 @@ static void tegra_gpio_enable(struct tegra_gpio_info *tgi, int gpio)
        tegra_gpio_mask_write(tgi, GPIO_MSK_CNF(tgi, gpio), gpio, 1);
 }

+static void tegra_gpio_disable(struct tegra_gpio_info *tgi, int gpio)
+{
+       tegra_gpio_mask_write(tgi, GPIO_MSK_CNF(tgi, gpio), gpio, 0);
+}
+
 static int tegra_gpio_request(struct gpio_chip *chip, unsigned offset)
 {
        tegra_gpio_save_gpio_state(offset);
@@ -225,8 +230,12 @@ static int tegra_gpio_request(struct gpio_chip *chip, unsigned offset)

 static void tegra_gpio_free(struct gpio_chip *chip, unsigned offset)
 {
+       struct tegra_gpio_info *tgi = gpiochip_get_data(chip);
+
        pinctrl_free_gpio(chip->base + offset);
        tegra_gpio_restore_gpio_state(offset);
+       tegra_gpio_disable(tgi, offset);
+
 }

 static void tegra_gpio_set(struct gpio_chip *chip, unsigned offset, int value)

2. Add below to the device tree.

               gpio_default: default {
+                       gpio-hog;
+                       function;
+                       gpios = <TEGRA_GPIO(C, 0) 0 TEGRA_GPIO(C, 1) 0 TEGRA_GPIO(C, 2) 0 TEGRA_GPIO(C, 3) 0 TEGRA_GPIO(C,4) 0>;

3. modify the pinmux in device tree like "spi1_miso_pc1 " …

[guoyj]

To help others debug SPI0 withe the eMMC module, Let me summarize the process:
For r32.4.3 emmc version

1. Modify the following files according to the contents of the patch package, tegra210-porg-gpio-p3448-0002-b00.dtsi tegra210-porg-pinmux-p3448-0002-b00.dtsi tegra210-porg-p3448-common.dtsi
   jetson-nano-support/l4t-sources-kernel-hardware-nvidia-platform-t210-porg-spidev0-0.patch at master · gtjoseph/jetson-nano-support · GitHub

2. Apply the kernel patch for GPIO to build the Image and replace it.

commit 7035ec4c1c3de0535f8491c1ca96814325bd8fc4
Author: snchen snchen@nvidia.com
Date: Fri Sep 6 15:56:47 2019 +0800

gpio: tegra: fix failed to set the to SFIO

Can't set the GPIO pin to SFIO by device tree.

bug 200549751

Change-Id: Idd331a594cb82b3a5ea4fc47c2784490ff99629f
Signed-off-by: snchen <snchen@nvidia.com>

diff --git a/drivers/gpio/gpio-tegra.c b/drivers/gpio/gpio-tegra.c
index e101044…09dd6e4 100644
— a/drivers/gpio/gpio-tegra.c
+++ b/drivers/gpio/gpio-tegra.c
@@ -217,6 +217,11 @@ static void tegra_gpio_enable(struct tegra_gpio_info *tgi, int gpio)
tegra_gpio_mask_write(tgi, GPIO_MSK_CNF(tgi, gpio), gpio, 1);
}

+static void tegra_gpio_disable(struct tegra_gpio_info *tgi, int gpio)
+{

•   tegra_gpio_mask_write(tgi, GPIO_MSK_CNF(tgi, gpio), gpio, 0);
  

+}
+
static int tegra_gpio_request(struct gpio_chip *chip, unsigned offset)
{
tegra_gpio_save_gpio_state(offset);
@@ -225,8 +230,12 @@ static int tegra_gpio_request(struct gpio_chip *chip, unsigned offset)

static void tegra_gpio_free(struct gpio_chip *chip, unsigned offset)
{

•   struct tegra_gpio_info *tgi = gpiochip_get_data(chip);
  

•   pinctrl_free_gpio(chip->base + offset);
    tegra_gpio_restore_gpio_state(offset);
  

•   tegra_gpio_disable(tgi, offset);
  

}

static void tegra_gpio_set(struct gpio_chip *chip, unsigned offset, int value)

3)Flash the kernel and dtb again.

[354236533]

81/5000
For r32.4.3 EMMC version, I modified kernel GPIO and device tree, but did not modify Uboot and still did not work. Could you please tell me how to use THE SPI function of R32.4.3 EMMC version

[ShaneCCC]

EMMC version just need configure by the jetson-io.py that should be working without modified the uboot.

[anhuimain]

Blockquote

Hi, @guoyj @354236533 have you make spi work on r32.4.3 emmc version?
I just follow above steps to enable spi1, but the spi1 sck pin23 keeps high.
Thanks

[anhuimain]

Hi, @ShaneCCC

I just follow above steps to change kernel and device tree, but the spi1 still not work.

The pin23 spi1 sck does not give periodical waveform and keeps high.

tegra_gpio shows

C: 0:2 08 08 08 08 00 00 000000

it's ok

and 

cat /proc/device-tree/pinmux@700008d4/common/spi1_sck_pc2/nvidia\,function

it shows spi1

it should be ok too!

The i use devmem2 read 0x70003058, 0xe045 read back. 
The register still keeps  at value 10 ("rsvd1"  not "spi1"),
But sd card nano read back 0xe044, that value represent the register is changed to spi1.

Can device tree change this pin-function correctly on emmc nano? Is there anything i missed?
		spi1_sck_pc2 {
 				nvidia,pins = "spi1_sck_pc2";
-				nvidia,function = "rsvd1";
+				nvidia,function = "spi1";
 				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
 				nvidia,tristate = <TEGRA_PIN_DISABLE>;
 				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
 
Using  devmem2  can enable spi1 and spi2 by comparing the reg value with sd card version module.

But modifying device tree is more straight, we just hope enable spi through device tree.

Can you give more suggestion?

Thanks

[elieva.pignat]

Hi, I am also trying to use the SPI on r32.4.3 eMMC jetson nano. Applying the patch and modifying the device tree were not enough and I did not manage to make it works. @ShaneCCC, jetson-io.py does not seem to work on eMMC version (it just open quickly and close).

@anhuimain

Using devmem2 can enable spi1 and spi2 by comparing the reg value with sd card version module.

Maybe someone knows how devmem2 can be used to enable spi1 and spi2?

[anhuimain]

hi @elieva.pignat

enable spi1

sudo ./devmem2 0x70003050 h 0xe044
sudo ./devmem2 0x70003054 h 0xe044
sudo ./devmem2 0x70003058 h 0xe044
sudo ./devmem2 0x7000305c h 0xe048
suod ./devmem2 0x70003060 h 0xe048

you should also apply the gpio kernel patch
and
add something like below maybe unnecessary (i just added it)

     spi@7000d400 { /* SPI 1 to 40 pin header */
              status = "okay";

•          num-cs = <1>;
  

•   cs-gpios = <&gpio TEGRA_GPIO(C, 3) GPIO_ACTIVE_LOW>;
  

•   spi0_0 {
  

•   	#address-cells = <0x1>;
  

•   	#size-cells = <0x0>;
  

•   	compatible = "spidev";
  

•   	status = "okay";
  

•   	reg = <0>;
  

•   	spi-max-frequency = <65000000>;
  

•   	controller-data {
  

•   		nvidia,cs-setup-clk-count = <0x1e>;
  

•   		nvidia,cs-hold-clk-count = <0x1e>;
  

•   		nvidia,rx-clk-tap-delay = <0x1f>;
  

•   		nvidia,tx-clk-tap-delay = <0x0>;
  

•   	};
  

•   };
  

  };

[anhuimain]

hi @elieva.pignat

enable spi2

I just test spi2 sck pin13, and get waveform from the pin .

sudo ./devmem2 0x6000d004 h 0x0000
sudo ./devmem2 0x70003064 h 0x6044
sudo ./devmem2 0x70003068 h 0x6044
sudo ./devmem2 0x7000306c h 0x6044
sudo ./devmem2 0x70003070 h 0x6048
suod ./devmem2 0x70003074 h 0x6048

[elieva.pignat]

Thanks @anhuimain !
I tested for spi2 with your command and it works!! I tested on a custom board where the spi is directly connected to the devices (and not through the 40-pin headers).

[libsong]

@ShaneCCC
Hi,

I used the patch and could see spi device in /dev/,
but seems the spi speed was abnormal.
when i test with 5M baudrate the data was ok, but when baudrate over than ~5M some data missed.
I use the emmc nano and l4t 32.4.4 with attachment patch.
0001-enable-spi2-device-0-and-no-hw-cs.patch (5.0 KB)

And use spidev_test to have spi loop test, the speed can not reach what i setted.
for example, ./spidev_test -s 8000000, but measured speed was 2000000.

any suggests?
tks.

[ShaneCCC]

Could you check the spi-max-frequency in the device tree?

[libsong]

@ShaneCCC
tks for your quick response.
the spi-max-frequency = <33000000>;
I had not modify it in dts as origin value.

tks.

[ShaneCCC]

Could you enable the debug print in the spi-tegra114.c and looks like the max speed is 25M

 	if (of_property_read_u32(pdev->dev.of_node, "spi-max-frequency",
  				 &master->max_speed_hz))
  		master->max_speed_hz = 25000000; /* 25MHz 

[libsong]

@ShaneCCC
Hi,
looks like the dts spi-max-frequency is useless, printk the value of tspi->master->max_speed_hz read from dts is always 0. So this is the reason why set it in code?

but seems it’s no relationship with what i saw, i just want a max 9M speed.
tks.

[ShaneCCC]

Could you enable the dev_dbg() to check the speed here.

static int tegra_spi_setup(struct spi_device *spi)
759  {
760  	struct tegra_spi_data *tspi = spi_master_get_devdata(spi->master);
761  	u32 val;
762  	unsigned long flags;
763  	int ret;
764  
765  	dev_dbg(&spi->dev, "setup %d bpw, %scpol, %scpha, %dHz\n",
766  		spi->bits_per_word,
767  		spi->mode & SPI_CPOL ? "" : "~",
768  		spi->mode & SPI_CPHA ? "" : "~",
769  		spi->max_speed_hz);

[libsong]

got below:

tks

[libsong]

@ShaneCCC
Hi,
had a test with code,

static void spi_write_msg(int fd, char const* tx, char const* rx, size_t len)
{
struct spi_ioc_transfer tr[2];

memset(tr, 0, sizeof tr);
tr[0].tx_buf = (unsigned long)tx;
tr[0].rx_buf = 0;
tr[0].len = len;
tr[0].speed_hz = spi_speed;

tr[1].tx_buf = 0;
tr[1].rx_buf = (unsigned long)rx;
tr[1].len = len;
tr[1].speed_hz = spi_speed;

if (ioctl(spi_fd, SPI_IOC_MESSAGE(2), &tr) < 1)
    pabort("can't send spi message");

}

I saw the gap between two spi transfer msg can reach hundreds of microseconds.

and debug in your driver static int tegra_spi_transfer_one_message(struct spi_master *master, struct spi_message *msg) function, can’t see what happen.
could you help me?
how can i decrease the gap between two transfer msg?

tks

[ShaneCCC]

@libsong
Looks like you were created new topic.

How to decrease the delay between spi transfer?

Hi all, I test the spi speed and found the gap between transfer is abnormal. had patched Bug200580239 Bug3053593 patch file in the How to decrease the delay between spi transfer and CS action? - #10 by zyxhuo. used dts of spidev0 as below: [图片] test transfer tx and rx with one byte four times. [图片] [图片] and the gap as below, could be ~1.5ms [图片] test with SPI_IOC_MESSAGE(2), [图片] [图片] and the gap still be ~350us, [图片] is anyone who can help me? where is my wrong? tks