Supported Baud Rates for the Sensor Processing Engine (SPE) UARTC

Hello,

I’m using the SPE UARTC to read data from a sensor which is configured for 460800 bps. The data I’m reading appears to be corrupted. What BAUD rates are supported by the SPE? I’m using the uart-tegra driver and modeled my code after uart-app.c in the rt-aux-cpu-demo.

Thanks,

Hi,
Please check this discussion thread:
https://devtalk.nvidia.com/default/topic/1058737/
The limitation is ~ 7.3Mbps. 460800bps looks fine. Please run cat /sys/kernel/debug/bpmp/debug/clk/clk_tree to get rate of usrtc.

This post probably helps:
https://devtalk.nvidia.com/default/topic/1031423/jetson-tx2/uart-ttyths2-be-blocked/post/5308801/#5308801
FYR.

I’m using the Sensor Processing Engine, so I’m not sure those other posts are going to be helpful. The device tree has uartc removed from the CCPLEX so I can use it with the SPE. I’m following the instruction in the Jetson Sensor Processing Engine (SPE) Developer Guide
r32.2 Release
, UART application (app/uart-app.c) section. How do I configure the UARTC clock for the SPE?

$ sudo cat /sys/kernel/debug/bpmp/debug/clk/clk_tree | grep uartc
	uartc			enabled: 0	refcounts: 0,0,	rate: 6981819

Is rate suppose to be divisible by 460800?

So those links did help, thanks! The clock was off by 11%, so I adjusted the bps setting to

struct tegra_uart_conf uart_conf = {
		.parity = TEGRA_UART_NO_PARITY,
		.stop_bits = TEGRA_UART_STOP_BITS_1,
		.data_bits = TEGRA_UART_DATA_BITS_8,
		.baud = 514483,
//		.baud = 460800,
	};

and it worked. Unfortunately this is an unacceptable hack. Any ideas how to fix it properly?

Hi,
Please measure the signal clock when you set to .baud = 460800. It is possible the clock source(PLLP) cannot be divided into the exact 460800. It looks fine to set to a bit higher clock value.

When measured with a scope, the baud rate is 412876 bps when .baud = 460800. How do I adjust the PLLP source? What other subsystem will adjusting the PLLP effect?

Hi,

As its already mentioned, its possible that based on divisor the actual baud rate may be settled to a lesser value. This happens when the divisor is set by either on lower or upper bound of the actual required divisor.

For example:
Source clock Rate: 408 MHz
Required Baud Rate: 4 M
Required Baud Frequency: 64 MHz
Actual Divisor Needed: 6.375
Recommended Baud Frequency: 65.28 MHz
New Divisor Needed: 6.25
Nearest Possible Div (lower side): 6
Nearest Possible Baud Frequency: 68 MHz
Baud Error: 6.25 %
Nearest Possible Div (Upper side): 6.5
Nearest Possible Baud Frequency: 62.76923077 MHz
Baud Error: -1.923076923 %

Another suggestion to reduce the error can be by changing the clock source.
Please check with PLLC_OUT0 instead of PLLP.
Let us know if you still have the issue.

Thanks & Regards,
Sandipan