As its already mentioned, its possible that based on divisor the actual baud rate may be settled to a lesser value. This happens when the divisor is set by either on lower or upper bound of the actual required divisor.
Source clock Rate: 408 MHz
Required Baud Rate: 4 M
Required Baud Frequency: 64 MHz
Actual Divisor Needed: 6.375
Recommended Baud Frequency: 65.28 MHz
New Divisor Needed: 6.25
Nearest Possible Div (lower side): 6
Nearest Possible Baud Frequency: 68 MHz
Baud Error: 6.25 %
Nearest Possible Div (Upper side): 6.5
Nearest Possible Baud Frequency: 62.76923077 MHz
Baud Error: -1.923076923 %
Another suggestion to reduce the error can be by changing the clock source.
Please check with PLLC_OUT0 instead of PLLP.
Let us know if you still have the issue.
Thanks & Regards,