Tegra K1 USB 3.0 Compliance Test Tools Availability

Robotics & Edge Computing Jetson & Embedded Systems Jetson TK1
1

Hello,

We have the document “TegraK1_USB2.0_Compliance_Test_AppNote_DA0719007.pdf” for USB 2.0 compliance testing.(Test J, Test K pattern)
Is there any reference or tool for the USB 3.0 compliance test procedure for TK1.

Regards,
Ankit

2

Hi, you can try below steps:

  1. Before test, the power control settings need to be ON in order to prevent USB xHCI controller from going to sleep during the test. From the shell, enter the following commands.
    echo on > /sys/bus/usb/devices/usb1/power/control
    echo on > /sys/bus/usb/devices/usb2/power/control

  2. The compliance registers must be set after USB 3.0 test fixture connected to Tegra, checking registers as below.
    T_XUSB_XHCI_OP_PORTSC[8:5] = Ah (TX)/ 05h (RX)
    T_XUSB_XHCI_EC_DBCAP_DCPORTSC[8:5] =Ah (TX)/ 05h (RX)

You can refer to the doc of TX1 and TK1 TRM for register address and other procedure setting: [url]https://developer.nvidia.com/embedded/dlc/tx1-usbss-compliance[/url]

3

Hi,

Thanks for the inputs.
I think as per your inputs USB3.0 Host Test Fixture hardware is required right?

I am looking for the same solution like
[url]https://devtalk.nvidia.com/default/topic/1008479/jetson-tx1/how-specify-xusb-register-address/1[/url]
This is to test electrical compliance test(TEST_J,TEST_K etc.) for USB 2.0

I want to test electrical compliance test for USB 3.0(CP0 or CP1 etc.)

Do you have any idea on that?

Regards,
Ankit

4

I cannot set T_XUSB_XHCI_OP_PORTSC(0x70090420) = 0x0A.
“devmem2 0x70090420 w 0x10340” command executed successfully, but when i read back the register “0x70090420” , it is returtned “0x2A0”.

Is there any other register need to set before this?

Regards,
Ankit

5

Hello,

Is there any updates on this?

Regards,
Ankit

6

We are checking internally, will feedback once available, thanks.