There is some conflicttion about the description of the Pcie Control signal like PEX_L0_CLKREQ_N.etc
In the OEM design guide Page 26 ，the signal is CMOS 1.8V，but in page 36，the signal is pulled up to VDDIO_AO_3V3？which page is right？
It’s 3.3V.
3Q，HaHa!