hi nvidia:
jp7.2 thor T5000 spi1(Bus 1: /dev/spidev1.0 => spi1: c6c0000.spi => SPI2 (PCC.07, PDD.00, PDD.01, PDD.02))最低可以输出多少兆clock ?
我设置2M clk，但是输出的是4.67M，但是我如果设置5M或者10M都可以按照设置值输出clk
Hi baierpo,
Are you using the devkit or custom board for Thor?
What’s the Jetpack version in use?
The 2 MHz setting is being rounded up because this SPI controller (c6c0000.spi / SPI2) cannot output lower than about 4.67 MHz with the current parent clock configuration.
SPI2 uses the divider formula Divide by (N/2 + 1) with an 8-bit divisor, and if the parent clock is PLLAON at about 600 MHz, the minimum clock is about 600 / 128.5 = 4.67 MHz.
That is why setting 2 MHz gives about 4.67 MHz, while 5 MHz and 10 MHz can match the requested value.
If you need a lower SPI clock, you need to change the SPI2 parent clock source / clock tree configuration.
You can simply run the following command to check:
# cat /sys/kernel/debug/bpmp/debug/clk/spi2/parent
# cat /sys/kernel/debug/bpmp/debug/clk/spi2/min_rate