硬件：T5000 + 自研载板
软件：Jetpack7.2 + 自己编译的内核
现象：ttyAMA10连接一个单片机，驱动和app需要同时访问ttyAMA10，代码在Jetpack7.1上运行正常。由于Jetpack7.2收紧了SMMU/IOMMU策略，使得驱动中对串口的kernel_write出现异常（如下）
需求：禁用ttyAMA10上的DMA，避免触发以下错误
[ 1370.281496] tegra-mc 8108020000.memory-controller: ptcr: @0x0000000000000000: Read response with poison bit error status:0
[ 1370.281528] tegra-mc 8108020000.memory-controller: gpcdmar: non-secure read @0x0000fffffffff000: EMEM address decode error (EMEM decode)
[ 1370.293318] tegra-mc 8108020000.memory-controller: gpcdmaw: non-secure write @0x0000fffffffff000: EMEM address decode error (EMEM decode)
Hi hyla_huang1,
Please share the full dmesg and device tree for further check.
You can try removing dma related properties in serial@810c540000 for this use case.
我尝试移除了serial@810c540000中dma相关的配置，确实不会再触发以上的错误。
但是，修改之后ttyAMA10就不通了，启动后波特率为9600，但即使手动stty或者在软件重新配置了波特率也仍然不通。应该怎样恢复ttyAMA10的正常通信？
附上禁用dma之后的fdt反编译结果和dmesg
dmesg.txt (124.3 KB)
fdt.dts.txt (332.1 KB)
Could you try updating the compatible string to use serial-tegra driver instead?
serial@810c540000 {
- compatible = "arm,pl011\0arm,primecell";
+ compatible = "nvidia,tegra194-hsuart";
尝试做这个tegra194的修改后，找不到ttyAMA10了。后附dmesg和fdt
root@M114:/home/vivibit# ll /dev/ttyAMA10
ls: cannot access ‘/dev/ttyAMA10’: No such file or directory
root@M114:/home/vivibit#
dmesg.194.txt (124.1 KB)
fdt.194.dts.txt (332.4 KB)
It is expected since you use different UART driver.
It may become ttyTHS10 instead.
[ 6.178309] serial-tegra 810c540000.serial: RX in PIO mode
[ 6.181825] serial-tegra 810c540000.serial: TX in PIO mode
[ 6.187566] serial-tegra 810c540000.serial: Failed to add uart port, err -22
[ 6.194370] serial-tegra: probe of 810c540000.serial failed with error -22
In the dmesg you shared, it seems the driver probing failed.
Maybe you need to keep using arm,pl011 driver but disable dma related properties.
I’m not clear why you have nvidia,disable-dma; in device tree.
Please just remove dma-names and dmas as following to verify.
serial@810c540000 {
iommus = <0x50 0x80c>;
arm,primecell-periphid = <0x51011>;
dma-coherent;
clock-names = "uartclk\0apb_pclk";
assigned-clocks = <0x02 0x33>;
assigned-clock-parents = <0x02 0x16>;
resets = <0x02 0x53>;
interrupts = <0x00 0xad 0x04>;
clocks = <0x02 0x33 0x02 0x16>;
- dma-names = "rx\0tx";
compatible = "arm,pl011\0arm,primecell";
status = "okay";
reg = <0x81 0xc540000 0x00 0x10000>;
phandle = <0x29c>;
- dmas = <0x132 0x0c 0x0c 0x80c 0x132 0x0c 0x16 0x80c>;
reset-names = "serial";
name = "serial";
};
If you still hit UART transaction issue with 9600 baudrate, please provide the result of the following commands.
sudo cat /sys/kernel/debug/clk/clk_summary | grep uart
sudo cat /sys/kernel/debug/bpmp/debug/clk/uart10/rate
It may be caused from low clock rate.
仅去掉dma-nanmes和dmas后的情况，后附dmesg和dt
root@M114:/home/vivibit# stty -F /dev/ttyAMA10
speed 9600 baud; line = 0;
-brkint -imaxbel
root@M114:/home/vivibit#
root@M114:/home/vivibit# cat /sys/kernel/debug/clk/clk_summary | grep uart
uart10 1 1 0 153583 0 0 50000 Y 810c540000.serial no_connection_id
uart9 1 1 0 388675 0 0 50000 Y 810c530000.serial no_connection_id
uart5 1 1 0 388675 0 0 50000 Y 810c510000.serial no_connection_id
uart0 0 0 0 1832579 0 0 50000 Y deviceless no_connection_id
uart8 0 0 0 27000000 0 0 50000 Y deviceless no_connection_id
uart4 0 0 0 27000000 0 0 50000 Y deviceless no_connection_id
root@M114:/home/vivibit#
root@M114:/home/vivibit# cat /sys/kernel/debug/bpmp/debug/clk/uart10/rate
153583
root@M114:/home/vivibit#
fdt.dts.202607221113.txt (332.2 KB)
dmesg.202607221113.txt (123.6 KB)
Please configure the clock rate for uart10 as 202.5MHz with the following commands to verify.
echo 0 > /sys/kernel/debug/bpmp/debug/clk/uart10/state
echo 202500000 > /sys/kernel/debug/bpmp/debug/clk/uart10/rate
echo 0 > /sys/kernel/debug/bpmp/debug/clk/uart10/state