Looking at the carrier board schematic specifically the connections:
I2C_GP0 - Pins E15/D15 - Open Drain 1.8V
I2C_GP1 - Pins A21/A20 - Open Drain 3.3V
I2C_PM - Pins A6/B6 - Open Drain 1.8V
POWER_BTN# - PIn B50 - Open Drain 1.8V
RESET_IN# - PIn A47 - Open Drain 1.8V
They are listed as open drain but on the carrier board none of them have a pull-up resistor on them. Is there already one on the TX1 SOM and if so it is pulled to the voltage that is listed?
I have not traced it down on schematics, but there is a level converter in the middle, which probably provides those pullups internally. J24 selects the 3.3V or 1.8V I/O indirectly through this mechanism.
J24 only select translation for a couple of peripherals mainly being AUDIO_I2S and SPI1 and has nothing to do with the signals I asked about.
So back to my original question. For instance the POWER_BTN is crucial to turning on the SOM. It is specified in the datasheet as being Open Drain 1.8V. When power is off and the SOM is in sleep mode there is no power on the carrier board at this point to feed the open drain. On the development platform carrier board there is no pull up on this pin only a contact to GND when the button is pressed. There must be some type of pull-up on the SOM for this to happen otherwise it would not work. Looking at the pinmux excel spreadsheet it looks like there is a selection for internal pull-up so this must be the mechanism that makes this possible.
Back to I2C_GP0 it shows in the pinmux an option for it to be 3.3V tolerant. In the datasheet it is specified as being open drain 1.8V. Can this be selected as a 3.3V tolerant input like I2C_GP1. I am currently translating I2C_GP0 but does that have to be the case?
I see on the P2597_B2_OrCAD_schemtics.pdf external reference “22” (looks like BGA pin D8 through J13) supplies power to much of this. For example, POWER_BTN_R on page 33 uses this. Voltage there is maintained by a zener diode at 5V, so the power source pull up must be at or greater than 5V via D8. Unfortunately, the pin is listed as “RSVD”, so I have no idea what is actually there. Assuming this really is connected directly to the TX1 BGA though, and that a zener is pulling this to ground at 5V without extra resistors, then the pull up has to be built directly into the TX1 chip. If it were known which power rail is used for BGA D8, then the resistor could be directly measured between that power bus and J6 pin 1.
Could someone with the internal layout information for BGA D8 comment on which power rail is used and with what pull-up resistor value?
POWER_BTN is connected to EN0(ONKEY) pin of PMU on CV-M board, it has a 10k PU to VDD_5V0_SYS, which never be turned off.
Each I2C has PU on CV_M board, that makes open drain work, if do not want to use default voltage,it needs to add level shift.
Hi everyone,
This topic seems to be the most relevant for my questions :
What about reset pins (RESET_IN# & RESET_OUT#) ?
In the document “JetsonTX1_OEM_Product_DesignGuide-1000010-13.pdf” I’ve noticed some incoherences :
*page 15 :
RESET_IN# is said to be on A46…is on A47 in the Jetson TX1 schematic (“P2597_B02_Concept_schematics.pdf” page 4)
RESET_OUT# is said to be on A47…is on A46 in the Jetson TX1 schematic (“P2597_B02_Concept_schematics.pdf” page 4)
same inversion for the chart below the synoptic.
We find other information about those pin on the same document page 53 (with JTAG explanation).
=> the pinout of them seems to be the right one here… Can somebody from NVIDIA confirm ?
Second question about them : which one is wired to the TX1 and which one is wired to the MAX77620 ?
If we invert RESET_IN# and RESET_OUT# nets on page 15 (to have the right pinout) it leads to a system with RESET_IN# on PMIC and RESET_OUT# on EMMC + TEGRA (maybe not represented devices like SPI Flash or EEPROM too ???)
If we look RESET_IN# and RESET_OUT# nets on page 53 we have a system with RESET_IN# on Tegra X1 and RESET_OUT# on PMIC (maybe not represented devices like SPI Flash or EEPROM too ???)
Last question is : can someone confirm that the diode between those two pins aim is to assert (active low) RESET_OUT# when RESET_IN# is asserted (active low) from Carrier board ?
Have a nice day,
Ale
I had not seen that discrepancy with RESET_IN# and RESET_OUT#. Good catch. I am curious about it as well.
If you look at the Jetson_TX1_Generic_Customer_Pinmux_Customer_Release.xlsm and the JetsonTX1_Module_Datasheet it has them like the schematic
RESET_IN# - A47
RESET_OUT# - A46
On another note regarding the I2C ports for the NVIDIA people. Do any of them have a pull-up’s on the SOM?
Hi snageli,
If you look on the OEM page 48, you can see all I²C are pulled up with 1k resistor on each line (1k to be OK with all speeds up to 3.4 Mbps (High speed mode).
For the reset, NV_Dusty answered it on this thread :
https://devtalk.nvidia.com/default/topic/913019/jetson-tx1/-hw-power-sequence-amp-reset-pins/?offset=5
So not anymore problems to develop a carrier board ;).
Regards,
Ale