TX1 Developer board Schematics

Where are the schematics for the TX1 developer board? You have the TK1 board schematics but not the TX1. The reason that I bought the board was to use its interfaces. I can’t design an interface without knowing what it’s connected to.

Here are the Jetson TX1 design files, filtered in the downloads center: https://developer.nvidia.com/embedded/downloads#?tx=$product,jetson_tx1$hardware,design,schematics

Here’s a link to the devkit schematics: [url]http://developer.nvidia.com/embedded/dlc/jetson-tx1-developer-kit-carrier-board-schematic-layout[/url]
Here’s a link to the camera module schematics: [url]http://developer.nvidia.com/embedded/dlc/jetson-tx1-developer-kit-camera-module-schematic-and-layout-files[/url]


Hopefully this question isn’t quite as stupid as the one you answered graciously; on J26 there are what appears to be 2 CAN bus channels. I wasn’t able to find anything in the SOC or carrier documentation about CAN interfaces. Any clues as to what peripheral in the SOC these signals connect to or how to use them as GPIO?

Very observant, these signals are reserved in the schematics, but are not provided by TX1 in the current generation.
J26 pins 1,3,5,7,9 and 13,15,17,19,21 are designated no-connect in the carrier spec.

Hi Dusty,

Speaking of “reserved” pins I would like to have some clarifications.

What you are saying is that CAN0 & CAN1 peripherals are wired on the connector to the carrier board but not software supported by NVIDIA, right ?

Another reserved pins related question that comes to my mind is what about interfaces that seem to be unconnected on the processor ?
For example I2C_GP2, I2C_GP3 and other pins like LCD1_BLKT_PWM seem to be not connected to the TX1 on the module regarding the OEM design guide… could you confirm that ?

Last curiosity about this topic, why are UART4_TX & UART4_RX (module balls D5 & D8) brought on the carrier ? Aren’t they used by the Wi-Fi/BT module ?

Have a nice day,

dusty_nv, thanks

One more question. It took me a while to figure out that the TX1 development system uses a TX1 SOM and carrier board… I don’t have the nerve to disconnect the SOM but it appears that you are using an FMC HPC type connector on the SOM. Looking at the SOM data sheet can I assume that the “pin” designations are for this connector type? While it’s doubtful that you followed the FMC assignments it would be interesting to know that I could create my own interface. I don’t think that the folks at nVidia realize the level of interest potential customers have in using your SOC with an FPGA.

The reserved CAN signals are not connected on the module, carrier, or software in the current generation. In a future generation Jetson module, CANbus may (or may not) be provided by Tegra chip. Leave them as no-connects on your carrier today.

This is correct, these reserved signals are not connected on module and should not be connected on the carrier either. Should a future generation Jetson module have more I2C’s available from Tegra chip, the pins are already there, reserved for use.

It’s in case a future version of the Jetson module is built without WiFi/BT, then that UART4 (which is used today for WiFi/BT) could be available to use.

note: when designing carrier, please check table 5 from Section 3 of the OEM DG.
if a pin says “Not used” under the Usage/Description column, please don’t connect it on your carrier. It’s reserved for a potential future Jetson module.

Here’s a diagram from section 15 of the OEM DG which shows the pin orientation.
The mating connector P/N from Samtec is shown at the bottom (SEAM-50-02.0-S-08-2-A-K-TR).

External Media

Here’s an article and video that shows the ‘disconnected’ connector:

Very interesting Kangalow thank you.

Are you the one who did the video ?

I am curious to see how it is under the thermal transfert plate so if someone could make a video unscrewing the 2 screws under the module it would be great.


You shouldn’t remove the TTP or underside stiffener of your module (unless you want it to become a space model). It has various types of machine-applied paste, thermal pads, RVT compound, ect. underneath that should only be applied at the factory.

Here’s what it looks like underneath:

(click link for full size) http://devblogs.nvidia.com/parallelforall/wp-content/uploads/2015/11/JTX1_top_bottom.png

Are the schematics for the Tegra X1 SOM available as well?

No, they are not public.