TX2 Carrier board - HW related questions

Autonomous Machines Jetson & Embedded Systems Jetson TX2
1

Hello,

I’m designing a board on which the TX2 module will be used for video processing (and not as the main processing/managment unit on the card).

I have a few questions about the board connectivity and design (my board, which is the carrier board).

  1. which UART is the one that Tegra will use to output all the prints? is it UART0?
    what information will be output to UART1? I’m trying to realize if i should connect it fro debug.

  2. Is it necessary to use CTS/RTS of UART0 if I connect the interface to a debug connector?
    If not, can they be left NC? tie CTS to GND?

  3. Auto power on:

    1. is connecting CHARGER_PRSNT# pin to GND enough for it to work?
    2. In case of auto power on – how do I need to treat VIN_PWR_BAD#, POWER_BTN#? Are they ignored
      in the module?
    3. If we look at the power up sequence diagram in page 11 of OEM design guide, how will it look
      with auto power on?
    4. if I don’t use auto power on, can CHARGER_PRSNT# be left NC?

  4. VDD_RTC: can I leave not connected if I don’t use the battery?

  5. CLKREQ# signal: I don’t have this signal in my PCIe device. What does the module expect to see
    in this signal?

Thanks!

2

On the dev board the CTS/RTS is actually non-functional for the serial (console) port. Generally speaking though, CTS/RTS is a kind of hardware flow control which is not enforced and you can switch to software flow control and ignore this. As speeds go up (or as cable lengths or noise sources increase) CTS/RTS will become more important. Typically a short connect at or below 115200 will be the highest speed where you can completely ignore CTS/RTS (you can go faster than this without CTS/RTS if conditions are right). I always use it when possible (it’s a “good thing”), but I think it is a bug in the TX2 that CTS/RTS does not work for serial console.

3

Hi tohar,

There is OEM DG file in download center, you can find most answers in it, please check that first before the design.
[url]https://developer.nvidia.com/embedded/dlc/jetson-tx2-oem-product-designguide[/url]

UART0 is for log info output, UART1 is reserved for a connector or camera. CTS/RTS is not must, but don’t change its default pin status as they could be the strapping pins, you can find more details in OEM DG.

There is a specific chapter in OEM DG for auto power on function, please check that for all auto power on problems.

VDD_RTC is not must, please just leave a cap there if no battery.

If your PCIE device has no CLKREQ#, then how to inform PCIE controller in TX2 to output clock needed?

4

Hi Trumany,

I’m also developing a carrier board for the TX2 module. I don’t need VDD_RTC either. Can I leave that signal unconnected? I don’t really want to add a supercap or battery if it isn’t necessary.

Thanks!

5

Hi marc, yes, it can be unconnected.

6

Hi Trumany,

Thanks for your response.

All my questions were written after reviewing the OEM DG doc.
I’d really appriciate if you could refer to each of the questions about the Auto power on.

Thanks,
Tohar

7

  1. is connecting CHARGER_PRSNT# pin to GND enough for it to work?

    ->It can work but not suggest to pull the pin to GND all the time.

  2. In case of auto power on – how do I need to treat VIN_PWR_BAD#, POWER_BTN#? Are they ignored
    in the module?

    → Nothing need to do with them, just keep as default.

  3. If we look at the power up sequence diagram in page 11 of OEM design guide, how will it look
    with auto power on?

    ->In the sequence, you can take POWER_BTN# as CHARGER_PRSNT#, and t2~t4 > 300ms

  4. if I don’t use auto power on, can CHARGER_PRSNT# be left NC?

    → Yes, it is NC default.

8

Thanks Trumany!

I think i got all the information I need.

please let me add another question - on the MIPI CSI/DSI connectivity.

I’m connecting these interfaces to Xilnx’s MPSOC (on board FPGA).

Do they require any on board termination?

Thanks again,
Tohar

9

Not sure what’s the meaning of your ‘termination’. OEM DG has the impedance request for layout, if FPGA board can follow it that should be workable.

10

Hi,

I need some help with the connectivity of several signals.

  1. JTAG_GP0 - I realize that this signal is different than in TX1.
    in case i’m not using the JAG interface - can it be left NC?

  2. FAN_TACH - can be left NC?

  3. BATT_OC – why is it bidirectional?
    what ircuit is required?

Thanks in advance!
Toahr

11

I didn’t see this last time, but I thought I’d set the record straight:
RTS/CTS have nothing at all to do with cable length.

They are there so that the other end can signal whether their receive buffer is full or not.
No matter how long the cable is, it only depends on how fast you can clear the receive buffer on the other end.
(within reason – TTL serial can’t drive wires long enough to make the latency of electric transmission matter)

And, as already has been pointed out, they don’t do anything on the TX2.

12

My understanding is that with CTS/RTS there is also less of a problem with jitter. Trying to estimate the clock from a data line will top off at a lower frequency than with a separate CTS/RTS…a side effect even if not the main purpose.

I do still wonder what is going on with why CTS/RTS does not function on a TX2…half of the conversation accepts it, the other half does not.

13

The start of the start bit is the start of the clock.

CTS/RTS typcially stays high or low across many bytes (and usually/often don’t change at all) and thus cannot be used for any kind of clock reconstruction.

14
  1. Yes, it can be left NC
  2. Yes.
  3. It is input, please check doc Jetson_TX1_TX2_Battery_and_Charger_Design_Guidelines
15

hi,what’s the different between jtag and debug interface?

16

There is a “debug” header on the dev carrier board which is custom to the Jetson. There is also a 20-pin standard JTAG header for JTAG debuggers.

17

Hello again,
In the datasheet, page 60, there is a note that says the keepout areas around the holes on carrier board should be GND.

  1. Is that the same GND I’m connecting to the connector?
  2. Is there chasis GND inside the module?
  3. Ny board will have a heatsink (in adittion to TX2 heatsink), connected to CGND. If the module doesn’t have CGND, than both grounds will be connected (which i’m trying to avoid).
    Is that correct?

I hope my questions are not totally out of scope…
Thanks

18

Yes, this GND is the board GND and connected to heatsink.

19

Hi,
Thanks.

I’m returning to one of my previous questions, about the MIPI csi/dsi interfaces.
Where can i find the electrical specifications of that interface?
I need to know if i need AC coupling or any termination, or I can connect directly.

Thanks

20

Please check MIPI related specifications for the electrical characters, the CSI/DSI ports of Jetson is standard.