Hello,
I have the same problem. I have my own design for carrier board. TX2 gets into USB recovery mode by shorting the FORCE_RECOV# to GND and powering up the system. However when I use TX2i I cannot get into USB recovery mode in the same scenarioo.
I want to mention that I work in Auto-Power-On on my carrier so CHARGER PRSNT (pin A49) is connected to GND for TX2 and POWER BTN (pin B50) is floating for TX2i Auto-Power-On.
Am I missing soething here?
Thanks,
Avi
Hi, C02 version carrier board design is for TX2i, there is a little difference between C02 and B04 (for TX2 and TX2 4GB), you can check the TX2 serires OEM DG in DLC for that and please check this topic (https://devtalk.nvidia.com/default/topic/1047809/jetson-tx2/auto-power-on-with-c02-carrier-board/) for auto-power-on rework on C02 design.
Thank you for your reply. I am well aware of the difference between the C02 and the B04 versions. However TX2i should Auto-Power-On on B04 without a problem as written in NVIDIA OEM document section 4.8.2. All is needed is that the POWER_BTN# will be left floating:
4.8.2 Jetson TX2i Auto-Power-On Details
For Jetson TX2i, which uses a different PMIC (and does not have the circuitry on TX2 4GB to make it compatible to TX2), the
POWER_BTN# pin needs to be held high. The TX2i PMIC has a level sensitive on input, so to power automatically when the
main power is applied (Auto-Power-On), all that is required is for the POWER_BTN# pin to be pulled up. Since this pin is pulled
up on the module, it can be left unconnected for Auto-Power-On to be supported.
I do not need the power button functionality so I do not need to generate a level from the edge of the button. This pin is floating on my design as written above and pulled up internally on the module so I do not understand why it is not working.
Thanks,
Avi
Did you probe the power up sequence of auto-power-on? Is there any device attached on UART3_TXD (H10) or UART3_RTS (G10) pin?
The power sequence is OK. We deliver 12V to the SOM via our carrier board. When the 12V stables then our carrier set VIN_PWR_BAD_L high to the SOM. After about 150mSec the SOM set CARRIER_PWR_ON to High and only then we power the rest of our carrier. I do not know how to attach a picture to this message so if you can tell me I can attach it. Please note that TX2 works fine and it is the SAME power sequence for both TX2 and TX2i if you do NOT use power button.
UART3 pins are floating.
Thanks,
Avi
That’s weird…basically if CARRIER_PWR_ON goes high, the module system was ON already. Can you share the power-on related part schematic of you design for check?
Sure I can but how to share it with you? When I press the “Link” icon I get “” printed in the Reply and I do not see how to attache a file.
One more note that might be relevant: I tie both RESET_OUT and RESET_IN together because I wanted a full system reset and not just Tegra reset. I know they are connected internally with a diode so I think it should not be a problem (and it works fine with TX2).
If you hover your mouse over the quote icon in the upper right of one of your existing posts, then other icons will show up. The paper clip icon is for attaching files.
I’m sorry but I do not get the paper clip icon :-( All I get is this quote above. I use Chrome and I tried to use even Internet Explorer but still can not get the paper clip icon. Probably browser problem…
Is there any way I can send the files by email?
MAIN_POWER_12VSOM_5VCARRIER.pdf (111 KB)
SOM_CON_1_3.pdf (109 KB)
POWER_to_FPGA_and_ENABLE_to_SOM.pdf (162 KB)
Sorry. Here are the files:
1 - MAIN_POWER_12VSOM_5VCARRIER is the main 12V supply to the SOM and 5V supply to the carrier. The rest of this page is not relevant.
2 - POWER_to_FPGA_and_ENABLE_to_SOM shows the 12V_IN that after filltering generates 12V_MOD to the module. You can see U38 that generates the VIN_PWR_BAD_L signal. CARRIER_PWR_ON is delivered via Q6 to FET Q5. This circuit delivers the 5V to the carrier only after CARRIER_PWR_ON is valid. Ignore the rest of this page.
3 - SOM_CON_1_3 is the SOM connector page that is relevant.
Hi, did you try adding 4.7k pull-down on UART4_TX (D8) pin? Also please not tie RESET_OUT and RESET_IN together, there is a little difference in module on this between TX2i and TX2 module, not sure if it is the cause.
Regarding the power sequence, is #2 line ‘VIN_PWR_BAD_L’ and #3 ‘CARRIER_PWR_ON’? Did you have the sequence including RESET_OUT?
Pin D8 has internal 4.7K resistor on both TX2 and TX2i so I did not connect it on my carrier. See attached picture from section 13.7 in the JetsonTX2_Series_OEM_Product_Design_Guide manual. I guess there is no point in wiring another resistor on my carrier. I can do it if you think it is needed.
With regard to RESET_OUT and RESET_IN, I understand that you want me to drive from my FPGA only REST_OUT#, right?
Still please try adding a 4.7k pull-down on pin D8 following reference schematic.
Yes for RESET_OUT# control, to keep same to ref design.
There are no other findings in your partial schematic. Since you are using FPGA to control the power sequence, it should be very careful. Do you have complete auto-power-on power sequence (from first power on and including RESET_OUT#) similar as listed in OEM DG?
Problem is solved! Using just RESET_OUT# and disconnecting RESET_IN# solve the problem.
Thank you very much for your kind support.
Avi
Glad to hear that. Even it works, if possible, for better understanding root cause, can you help us to probe a whole power-on sequence in which the RESET_IN# and RESET_OUT# are tied together? It would be better to know if RESET_OUT# will go high in this situation, thanks.
We did the test as you requested. The RESET lines goes high when tied together (IN and OUT).
