tx2 - Camera mipi timing and PXL_SOF

Robotics & Edge Computing Jetson & Embedded Systems Jetson TX2
9

Below patch to disable payload CRC error check. And this sensor need modify embedded_metadata_height = “4”;
After this the v4l2-ctl should be able capture well.

diff --git a/drivers/media/platform/tegra/camera/csi/csi4_fops.c b/drivers/media/platform/tegra/camera/csi/csi4_fops.c
index 0377d7b..b3d01d3 100644
--- a/drivers/media/platform/tegra/camera/csi/csi4_fops.c
+++ b/drivers/media/platform/tegra/camera/csi/csi4_fops.c
@@ -76,8 +76,18 @@ static void csi4_stream_init(struct tegra_csi_channel *chan, int port_num)
        csi4_stream_write(chan, port_num, INTR_STATUS, 0x3ffff);
        csi4_stream_write(chan, port_num, ERR_INTR_STATUS, 0x7ffff);
        csi4_stream_write(chan, port_num, ERROR_STATUS2VI_MASK, 0x0);
-       csi4_stream_write(chan, port_num, INTR_MASK, 0x0);
-       csi4_stream_write(chan, port_num, ERR_INTR_MASK, 0x0);
+//     csi4_stream_write(chan, port_num, INTR_MASK, 0x0);
+//     csi4_stream_write(chan, port_num, ERR_INTR_MASK, 0x0);
+
+       csi4_stream_write(chan, port_num, INTR_MASK, PH_ECC_MULTI_BIT_ERR |
+                       PD_CRC_ERR_VC0 | PH_ECC_SINGLE_BIT_ERR_VC0);
+       csi4_stream_write(chan, port_num, ERR_INTR_MASK, PH_ECC_MULTI_BIT_ERR |
+                       PD_CRC_ERR_VC0 | PH_ECC_SINGLE_BIT_ERR_VC0);
+       csi4_stream_write(chan, port_num, ERROR_STATUS2VI_MASK,
+                       CFG_ERR_STATUS2VI_MASK_VC0 |
+                       CFG_ERR_STATUS2VI_MASK_VC1 |
+                       CFG_ERR_STATUS2VI_MASK_VC2 |
+                       CFG_ERR_STATUS2VI_MASK_VC3);
 }