tx2 - Camera mipi timing and PXL_SOF

Shane, this is another issue not the previous one, the previous one is fixed by modify dtsi file , this is PXL_SOF
issue . Can you help to identify some direction ? I 've tried all comibination of ths-settle or clk-settle .

set discontinous_clk have the same result .

Does v4l2-ctl working well?

Nope , this is the v4l2-ctl result.

On tx1 it works well , but on tx2 it is not. I searched through the forum on PIX_SOF issue , and tried all methods mentioned in post.

CRC issue is a common issue, it can be caused by:
• Sensor TX side send bad pixe/crc value.
• SI quality of the CSI channel.

Below patch to disable payload CRC error check. And this sensor need modify embedded_metadata_height = “4”;
After this the v4l2-ctl should be able capture well.

diff --git a/drivers/media/platform/tegra/camera/csi/csi4_fops.c b/drivers/media/platform/tegra/camera/csi/csi4_fops.c
index 0377d7b..b3d01d3 100644
--- a/drivers/media/platform/tegra/camera/csi/csi4_fops.c
+++ b/drivers/media/platform/tegra/camera/csi/csi4_fops.c
@@ -76,8 +76,18 @@ static void csi4_stream_init(struct tegra_csi_channel *chan, int port_num)
        csi4_stream_write(chan, port_num, INTR_STATUS, 0x3ffff);
        csi4_stream_write(chan, port_num, ERR_INTR_STATUS, 0x7ffff);
        csi4_stream_write(chan, port_num, ERROR_STATUS2VI_MASK, 0x0);
-       csi4_stream_write(chan, port_num, INTR_MASK, 0x0);
-       csi4_stream_write(chan, port_num, ERR_INTR_MASK, 0x0);
+//     csi4_stream_write(chan, port_num, INTR_MASK, 0x0);
+//     csi4_stream_write(chan, port_num, ERR_INTR_MASK, 0x0);
+       csi4_stream_write(chan, port_num, INTR_MASK, PH_ECC_MULTI_BIT_ERR |
+                       PD_CRC_ERR_VC0 | PH_ECC_SINGLE_BIT_ERR_VC0);
+       csi4_stream_write(chan, port_num, ERR_INTR_MASK, PH_ECC_MULTI_BIT_ERR |
+                       PD_CRC_ERR_VC0 | PH_ECC_SINGLE_BIT_ERR_VC0);
+       csi4_stream_write(chan, port_num, ERROR_STATUS2VI_MASK,
+                       CFG_ERR_STATUS2VI_MASK_VC0 |
+                       CFG_ERR_STATUS2VI_MASK_VC1 |
+                       CFG_ERR_STATUS2VI_MASK_VC2 |
+                       CFG_ERR_STATUS2VI_MASK_VC3);

Still no luck, the result is full of

[ 34.746302] tegra-vi4 15700000.vi: PXL_SOF syncpt timeout! err = -11.

We tried different embedded_metadata_height = 0 , 1,2,4 . Actually , from the sensor data sheet, the default
value will be 2 lines in the head and 2 lines in the tail . But if we disable or enable it , and with all
combinations of embedded_metadata_height . The result all have syncpt timeout.

The same code and config behaves well in tx1.

Does the trace still show CSIMUX_FRAME?

CSIMUX_FRAME channel:0x00 frame:1 vi_tstamp:3735249216 data:0x00400060

The trace as below.

kworker/0:2-287   [000] ...1    58.006268: rtcpu_vinotify_handle_msg: tstamp:2144938002 tag:ATOMP_FS channel:0x00 frame
:1 vi_tstamp:2144937588 data:0x00000000
     kworker/0:2-287   [000] ...1    58.006270: rtcpu_vinotify_handle_msg: tstamp:2144940489 tag:CHANSEL_PXL_SOF channel:0x0
0 frame:1 vi_tstamp:2144940045 data:0x00000001
     kworker/0:2-287   [000] ...1    58.006271: rtcpu_vinotify_handle_msg: tstamp:2144943165 tag:CHANSEL_LOAD_FRAMED channel
:0x04 frame:1 vi_tstamp:2144942757 data:0x08000000
     kworker/0:2-287   [000] ...1    58.058273: rtcpu_vinotify_handle_msg: tstamp:2145935231 tag:CHANSEL_PXL_EOF channel:0x0
0 frame:1 vi_tstamp:2145934516 data:0x031f0002
     kworker/0:2-287   [000] ...1    58.058276: rtcpu_vinotify_handle_msg: tstamp:2145935335 tag:CSIMUX_FRAME channel:0x00 f
rame:1 vi_tstamp:2145934539 data:0x00400062
     kworker/0:2-287   [000] ...1    58.058277: rtcpu_vinotify_handle_msg: tstamp:2145935524 tag:ATOMP_FE channel:0x00 frame
:1 vi_tstamp:2145934543 data:0x00000000

Still report the crc error looks like the crc mask didn’t set.
Have a read and print out those message to check.

Just ensure the crc mask work and device tree ok.
Now there is no syncpt timeout error , following is the trace

:1 vi_tstamp:4279367488 data:0x00000000
     kworker/3:1-53    [003] ...1   126.279631: rtcpu_vinotify_handle_msg: tstamp:4279370377 tag:CHANSEL_PXL_SOF channel:0x0
0 frame:1 vi_tstamp:4279369946 data:0x00000001
     kworker/3:1-53    [003] ...1   126.279632: rtcpu_vinotify_handle_msg: tstamp:4279373038 tag:CHANSEL_LOAD_FRAMED channel
:0x04 frame:1 vi_tstamp:4279372630 data:0x08000000
     kworker/3:1-53    [003] ...1   126.331638: rtcpu_vinotify_handle_msg: tstamp:4280365005 tag:CHANSEL_PXL_EOF channel:0x0
0 frame:1 vi_tstamp:4280364417 data:0x031f0002
     kworker/3:1-53    [003] ...1   126.331643: rtcpu_vinotify_handle_msg: tstamp:4280365109 tag:ATOMP_FE channel:0x00 frame
:1 vi_tstamp:4280364443 data:0x00000000
     kworker/3:1-53    [003] ...1   126.331646: rtcpu_vinotify_handle_msg: tstamp:4280402347 tag:ATOMP_FS channel:0x00 frame
:2 vi_tstamp:4280401928 data:0x00000000
     kworker/3:1-53    [003] ...1   126.331649: rtcpu_vinotify_handle_msg: tstamp:4280404803 tag:CHANSEL_PXL_SOF channel:0x0
0 frame:2 vi_tstamp:4280404386 data:0x00000001
     kworker/3:1-53    [003] ...1   126.331651: rtcpu_vinotify_handle_msg: tstamp:4280407201 tag:CHANSEL_LOAD_FRAMED channel
:0x04 frame:2 vi_tstamp:4280406792 data:0x08000000
     kworker/3:1-53    [003] ...1   126.331656: rtos_queue_peek_from_isr_failed: tstamp:4280982166 queue:0x0b4a3c58
     kworker/3:1-53    [003] ...1   126.383595: rtcpu_vinotify_handle_msg: tstamp:4281399471 tag:CHANSEL_PXL_EOF channel:0x0
0 frame:2 vi_tstamp:4281398857 data:0x031f0002
     kworker/3:1-53    [003] ...1   126.383603: rtcpu_vinotify_handle_msg: tstamp:4281399613 tag:ATOMP_FE channel:0x00 frame
:2 vi_tstamp:4281398883 data:0x00000000
     kworker/3:1-53    [003] ...1   126.383605: rtcpu_vinotify_handle_msg: tstamp:4281436809 tag:ATOMP_FS channel:0x00 frame
:3 vi_tstamp:4281436369 data:0x00000000
     kworker/3:1-53    [003] ...1   126.383608: rtcpu_vinotify_handle_msg: tstamp:4281439263 tag:CHANSEL_PXL_SOF channel:0x0
0 frame:3 vi_tstamp:4281438826 data:0x00000001
     kworker/3:1-53    [003] ...1   126.383611: rtcpu_vinotify_handle_msg: tstamp:4281443484 tag:CHANSEL_LOAD_FRAMED channel
:0x04 frame:3 vi_tstamp:4281443058 data:0x08000000
     kworker/3:1-53    [003] ...1   126.383613: rtcpu_vinotify_handle_msg: tstamp:4282433902 tag:CHANSEL_PXL_EOF channel:0x0
0 frame:3 vi_tstamp:4282433297 data:0x031f0002
     kworker/3:1-53    [003] ...1   126.383616: rtcpu_vinotify_handle_msg: tstamp:4282434039 tag:ATOMP_FE channel:0x00 frame
:3 vi_tstamp:4282433323 data:0x00000000
     kworker/3:1-53    [003] ...1   126.383619: rtcpu_vinotify_handle_msg: tstamp:4282471247 tag:ATOMP_FS channel:0x00 frame
:4 vi_tstamp:4282470809 data:0x00000000
     kworker/3:1-53    [003] ...1   126.383622: rtcpu_vinotify_handle_msg: tstamp:4282473707 tag:CHANSEL_PXL_SOF channel:0x0
0 frame:4 vi_tstamp:4282473266 data:0x00000001
     kworker/3:1-53    [003] ...1   126.383625: rtcpu_vinotify_handle_msg: tstamp:4282479238 tag:CHANSEL_LOAD_FRAMED channel
:0x04 frame:4 vi_tstamp:4282478809 data:0x08000000
     kworker/3:1-53    [003] ...1   126.435557: rtcpu_vinotify_handle_msg: tstamp:4283468344 tag:CHANSEL_PXL_EOF channel:0x0
0 frame:4 vi_tstamp:4283467736 data:0x031f0002
     kworker/3:1-53    [003] ...1   126.435561: rtcpu_vinotify_handle_msg: tstamp:4283468484 tag:ATOMP_FE channel:0x00 frame
:4 vi_tstamp:4283467762 data:0x00000000

However, the raw captured only have a few lines in the top , and others all black. Possible cause ? The values in devices tree like pix_clk_hz, mclk_multiplier is the same that worked in tx1.

Could you try the color pattern.

I mean the raw data , not pass ISP pipe line, is whole black, it shall not related to the color pattern.

Yes, I know not pass to ISP however still please set the sensor output color pattern to verify.

We changed the color pattern values, there is no difference on the result.
The weird thing we found is that we can only set embedded_metadata_height = “1”, we could have
output image instead of all black, and on this case , there is still timeout log. And from the
sensor datasheet, current we shall have embedded_metadata_height = “2”, is correct.

My config is embedded_metadata_height = “4” there’s no problem for me.
Did you build this sensor by yourself or buy it from vendor?

Can you share me your mode table for the sensor ?
What is value for register 0x3064 , Set it or leave it as default. We build the sensor board ourself.

And can you share me your device tree settings ?

static const ar0144_reg ar0144_mode_1280x720_30fps[] = {
        {0x301A, 0x00D9},
        {0x3088, 0x8000},
        {0x3086, 0x327F},
        {0x3086, 0x5780},
        {0x3086, 0x2730},
        {0x3086, 0x7E13},
        {0x3086, 0x8000},
        {0x3086, 0x157E},
        {0x3086, 0x1380},
        {0x3086, 0x000F},
        {0x3086, 0x8190},
        {0x3086, 0x1643},
        {0x3086, 0x163E},
        {0x3086, 0x4522},
        {0x3086, 0x0937},
        {0x3086, 0x8190},
        {0x3086, 0x1643},
        {0x3086, 0x167F},
        {0x3086, 0x9080},
        {0x3086, 0x0038},
        {0x3086, 0x7F13},
        {0x3086, 0x8023},
        {0x3086, 0x3B7F},
        {0x3086, 0x9345},
        {0x3086, 0x0280},
        {0x3086, 0x007F},
        {0x3086, 0xB08D},
        {0x3086, 0x667F},
        {0x3086, 0x9081},
        {0x3086, 0x923C},
        {0x3086, 0x1635},
        {0x3086, 0x7F93},
        {0x3086, 0x4502},
        {0x3086, 0x8000},
        {0x3086, 0x7FB0},
        {0x3086, 0x8D66},
        {0x3086, 0x7F90},
        {0x3086, 0x8182},
        {0x3086, 0x3745},
        {0x3086, 0x0236},
        {0x3086, 0x8180},
        {0x3086, 0x4416},
        {0x3086, 0x3143},
        {0x3086, 0x7416},
        {0x3086, 0x787B},
        {0x3086, 0x7D45},
        {0x3086, 0x023D},
        {0x3086, 0x6445},
        {0x3086, 0x0A3D},
        {0x3086, 0x647E},
        {0x3086, 0x1281},
        {0x3086, 0x8037},
        {0x3086, 0x7F10},
        {0x3086, 0x450A},
        {0x3086, 0x3F74},
        {0x3086, 0x7E10},
        {0x3086, 0x7E12},
        {0x3086, 0x0F3D},
        {0x3086, 0xD27F},
        {0x3086, 0xD480},
        {0x3086, 0x2482},
        {0x3086, 0x9C03},
        {0x3086, 0x430D},
        {0x3086, 0x2D46},
        {0x3086, 0x4316},
        {0x3086, 0x5F16},
        {0x3086, 0x532D},
        {0x3086, 0x1660},
        {0x3086, 0x404C},
        {0x3086, 0x2904},
        {0x3086, 0x2984},
        {0x3086, 0x81E7},
        {0x3086, 0x816F},
        {0x3086, 0x170A},
        {0x3086, 0x81E7},
        {0x3086, 0x7F81},
        {0x3086, 0x5C0D},
        {0x3086, 0x5749},
        {0x3086, 0x5F53},
        {0x3086, 0x2553},
        {0x3086, 0x274D},
        {0x3086, 0x2BF8},
        {0x3086, 0x1016},
        {0x3086, 0x4C09},
        {0x3086, 0x2BB8},
        {0x3086, 0x2B98},
        {0x3086, 0x4E11},
        {0x3086, 0x5367},
        {0x3086, 0x4001},
        {0x3086, 0x605C},
        {0x3086, 0x095C},
        {0x3086, 0x1B40},
        {0x3086, 0x0245},
        {0x3086, 0x0045},
        {0x3086, 0x8029},
        {0x3086, 0xB67F},
        {0x3086, 0x8040},
        {0x3086, 0x047F},
        {0x3086, 0x8841},
        {0x3086, 0x095C},
        {0x3086, 0x0B29},
        {0x3086, 0xB241},
        {0x3086, 0x0C40},
        {0x3086, 0x0340},
        {0x3086, 0x135C},
        {0x3086, 0x0341},
        {0x3086, 0x1117},
        {0x3086, 0x125F},
        {0x3086, 0x2B90},
        {0x3086, 0x2B80},
        {0x3086, 0x816F},
        {0x3086, 0x4010},
        {0x3086, 0x4101},
        {0x3086, 0x5327},
        {0x3086, 0x4001},
        {0x3086, 0x6029},
        {0x3086, 0xA35F},
        {0x3086, 0x4D1C},
        {0x3086, 0x1702},
        {0x3086, 0x81E7},
        {0x3086, 0x2983},
        {0x3086, 0x4588},
        {0x3086, 0x4021},
        {0x3086, 0x7F8A},
        {0x3086, 0x4039},
        {0x3086, 0x4580},
        {0x3086, 0x2440},
        {0x3086, 0x087F},
        {0x3086, 0x885D},
        {0x3086, 0x5367},
        {0x3086, 0x2992},
        {0x3086, 0x8810},
        {0x3086, 0x2B04},
        {0x3086, 0x8916},
        {0x3086, 0x5C43},
        {0x3086, 0x8617},
        {0x3086, 0x0B5C},
        {0x3086, 0x038A},
        {0x3086, 0x484D},
        {0x3086, 0x4E2B},
        {0x3086, 0x804C},
        {0x3086, 0x0B41},
        {0x3086, 0x9F81},
        {0x3086, 0x6F41},
        {0x3086, 0x1040},
        {0x3086, 0x0153},
        {0x3086, 0x2740},
        {0x3086, 0x0160},
        {0x3086, 0x2983},
        {0x3086, 0x2943},
        {0x3086, 0x5C05},
        {0x3086, 0x5F4D},
        {0x3086, 0x1C81},
        {0x3086, 0xE745},
        {0x3086, 0x0281},
        {0x3086, 0x807F},
        {0x3086, 0x8041},
        {0x3086, 0x0A91},
        {0x3086, 0x4416},
        {0x3086, 0x092F},
        {0x3086, 0x7E37},
        {0x3086, 0x8020},
        {0x3086, 0x307E},
        {0x3086, 0x3780},
        {0x3086, 0x2015},
        {0x3086, 0x7E37},
        {0x3086, 0x8020},
        {0x3086, 0x0343},
        {0x3086, 0x164A},
        {0x3086, 0x0A43},
        {0x3086, 0x160B},
        {0x3086, 0x4316},
        {0x3086, 0x8F43},
        {0x3086, 0x1690},
        {0x3086, 0x4316},
        {0x3086, 0x7F81},
        {0x3086, 0x450A},
        {0x3086, 0x4130},
        {0x3086, 0x7F83},
        {0x3086, 0x5D29},
        {0x3086, 0x4488},
        {0x3086, 0x102B},
        {0x3086, 0x0453},
        {0x3086, 0x2D40},
        {0x3086, 0x3045},
        {0x3086, 0x0240},
        {0x3086, 0x087F},
        {0x3086, 0x8053},
        {0x3086, 0x2D89},
        {0x3086, 0x165C},
        {0x3086, 0x4586},
        {0x3086, 0x170B},
        {0x3086, 0x5C05},
        {0x3086, 0x8A60},
        {0x3086, 0x4B91},
        {0x3086, 0x4416},
        {0x3086, 0x0915},
        {0x3086, 0x3DFF},
        {0x3086, 0x3D87},
        {0x3086, 0x7E3D},
        {0x3086, 0x7E19},
        {0x3086, 0x8000},
        {0x3086, 0x8B1F},
        {0x3086, 0x2A1F},
        {0x3086, 0x83A2},
        {0x3086, 0x7E11},
        {0x3086, 0x7516},
        {0x3086, 0x3345},
        {0x3086, 0x0A7F},
        {0x3086, 0x5380},
        {0x3086, 0x238C},
        {0x3086, 0x667F},
        {0x3086, 0x1381},
        {0x3086, 0x8414},
        {0x3086, 0x8180},
        {0x3086, 0x313D},
        {0x3086, 0x6445},
        {0x3086, 0x2A3D},
        {0x3086, 0xD27F},
        {0x3086, 0x4480},
        {0x3086, 0x2494},
        {0x3086, 0x3DFF},
        {0x3086, 0x3D4D},
        {0x3086, 0x4502},
        {0x3086, 0x7FD0},
        {0x3086, 0x8000},
        {0x3086, 0x8C66},
        {0x3086, 0x7F90},
        {0x3086, 0x8194},
        {0x3086, 0x3F44},
        {0x3086, 0x1681},
        {0x3086, 0x8416},
        {0x3086, 0x2C2C},
        {0x3086, 0x2C2C},

        {0x3ED6, 0x3CB5},
        {0x3ED8, 0x8765},
        {0x3EDA, 0x8888},
        {0x3EDC, 0x97FF},

        {0x3EF8, 0x6522},
        {0x3EFA, 0x2222},
        {0x3EFC, 0x6666},
        {0x3F00, 0xAA05},
        {0x3EE2, 0x180E},
        {0x3EE4, 0x0808},
        {0X3EEA, 0x2A09},
        {0x3060, 0x0000},

        {0x3092, 0x00CF},
        {0X3268, 0x0030},
        {0X3786, 0x0006},
        {0x3F4A, 0x0F70},
        {0x306E, 0x4810},
        {0x3064, 0x1802},
        {0x3EF6, 0x8041},
        {0x3180, 0xC08F},
        {0x30BA, 0x7623},
        {0x3176, 0x0480},
        {0x3178, 0x0480},
        {0x317A, 0x0480},
        {0x317C, 0x0480},

        {0x302A, 0x0006},
        {0x302C, 0x0001},
        {0x302E, 0x0004},
        {0x3030, 0x0042},
        {0x3036, 0x000C},
        {0x3038, 0x0001},

        {0x30B0, 0x0038},

        {0x31AE, 0x0202},
        {0x31AC, 0x0C0C},
        {0x31B0, 0x0042},
        {0x31B2, 0x002E},
        {0x31B4, 0x1665},
        {0x31B6, 0x110E},
        {0x31B8, 0x2047},
        {0x31BA, 0x0105},
        {0x31BC, 0x0004},

        {0x3002, 0x0028},
        {0x3004, 0x0004},
        {0x3006, 0x02F7}, //0x2f7
        {0x3008, 0x0503},

        {0x300A, 0x067F},
        {0x300C, 0x05D0},
        {0x3012, 0x0190},
        {0x30A2, 0x0001},
        {0x30A6, 0x0001},
        {0x3040, 0x0000},

        {0x3040, 0x0400},
        {0x30A8, 0x0003},
        {0x3040, 0x0c00},
        {0x30AE, 0x0003},
        {AR0144_TABLE_END, 0x00}
ar0144_a@10 {
                                        compatible = "nvidia,ar0144";
                                        reg = <0x10>;
                                        physical_w = "3.674";
                                        physical_h = "2.738";
                                        avdd-reg = "vana";
                                        iovdd-reg = "vif";
                                        dvdd-reg = "vdig";
                                        sensor_model = "ar0144";
                                        post_crop_frame_drop = [30 00];
                                        delayed_gain = "true";
                                        clocks = <0xd 0x59 0xd 0x10d>;
                                        clock-names = "extperiph1", "pllp_grtba";
                                        clock-frequency = <0x19bfcc0>;
                                        mclk = "extperiph1";
                                        reset-gpios = <0x12 0x8d 0x0>;
                                        vana-supply = <0x20>;
                                        vif-supply = <0x1f>;
                                        vdig-supply = <0x21>;

                                        mode0 {
                                                mclk_khz = "27000";
                                                num_lanes = [32 00];
                                                tegra_sinterface = "serial_a";
                                                discontinuous_clk = "yes";
                                                dpcm_enable = "false";
                                                cil_settletime = [30 00];

                                                dynamic_pixel_bit_depth = "12";
                                                csi_pixel_bit_depth = "12";
                                                mode_type = "bayer";
                                                pixel_phase = "rggb";

                                                active_w = "1280";
                                                active_h = "720";
                                                readout_orientation = [30 00];
                                                line_length = "1488";
                                                inherent_gain = [31 00];
                                                mclk_multiplier = "5.93";
                                                pix_clk_hz = "160000000";
                                                min_gain_val = [31 00];
                                                max_gain_val = "30";
                                                min_hdr_ratio = [31 00];
                                                max_hdr_ratio = "64";
                                                min_framerate = "30";
                                                max_framerate = "30";
                                                min_exp_time = "200";
                                                max_exp_time = "16653";
                                                embedded_metadata_height = [34 00];

Changed to the device tree and mode table, we could get raw image data. However, Seems some artifact in the
center, not quite sure if it is data corruption. Does your image correct under this configuration ?

A weird thing is that from the sensor data sheet R0x3064 -1802 does not mean 4 lines embeded data,but excluded embeddd data. We will confirm with sensor, and does your sensor mode table comes from them directly. It is quite different of yours and ours.