TX2 Jetpack 4.2 spidev3.1 configuration

I am trying to migrate from jetpack 3.3 to jetpack 4.2 I am having some issues with the SPI interfaces. I was able to follow the instructions in this post to get the spidev3.0 interface working. https://devtalk.nvidia.com/default/topic/1049999/spi-works-with-jetpack-3-3-but-not-jetpack-4-2/

However, I am unable to get the spidev3.1 interface working. I can’t figure out what I need to do to get the second chip select to work.

In the above thread ShaneCCC states that it is “It is float in module.” Idon’t know what that means.

Can someone please explain all the steps, device tree and or pinmux modifications, to enable the second chip select for spidev3.1. This chip select is pin 26 on J21 labeled “SPI_CE1_N SPI #1 Chip Select #1” according to jetson hacks.

https://www.jetsonhacks.com/nvidia-jetson-tx2-j21-header-pinout/

thank you for your help.

my device tree entry for spi3 is

spi3: spi@3240000 {
    compatible = "nvidia,tegra186-spi";
    reg = <0x0 0x03240000 0x0 0x10000>;
    interrupts = <0 39 0x04>;
    #address-cells = <1>;
    #size-cells = <0>;
    iommus = <&smmu TEGRA_SID_GPCDMA_0>;
    dmas = <&gpcdma 18>, <&gpcdma 18>;
    dma-names = "rx", "tx";
    nvidia,clk-parents = "pll_p", "clk_m";
    clocks = <&tegra_car TEGRA186_CLK_SPI4>,
        <&tegra_car TEGRA186_CLK_PLLP_OUT0>,
        <&tegra_car TEGRA186_CLK_CLK_M>;
    clock-names = "spi", "pll_p", "clk_m";
    resets = <&tegra_car TEGRA186_RESET_SPI4>;
    reset-names = "spi";
    status = "okay";
    spi@0 {
        compatible = "spidev";
        reg = <0x0>;
        spi-max-frequency = <0x1312D00>;
        nvidia,enable-hw-based-cs;
        nvidia,cs-setup-clk-count = <0x1e>;
        nvidia,cs-hold-clk-count = <0x1e>;
        nvidia,rx-clk-tap-delay = <0x1f>;
        nvidia,tx-clk-tap-delau = <0x0>;
    };
    spi@1 {
        compatible = "spidev";
        reg = <0x1>;
        spi-max-frequency = <0x1312D00>;
        nvidia,enable-hw-based-cs;
        nvidia,cs-setup-clk-count = <0x1e>;
        nvidia,cs-hold-clk-count = <0x1e>;
        nvidia,rx-clk-tap-delay = <0x1f>;
        nvidia,tx-clk-tap-delau = <0x0>;
    };
};

Hi tkuraku
The pin 26 on J21 labeled “SPI_CE1_N” in not connect to tegra. It’s floating pin. So you can’t use it as chip select for SPI3, You may need implement GPIO as chip select.

https://devtalk.nvidia.com/default/topic/1058604/jetson-tx2/multiple-tx2-spi-slave-select-with-gpio-in-dtb-/post/5372349/#5372349