TX2 NX - Cannot use certain GPIO with sysfs or libgpiod

Autonomous Machines Jetson & Embedded Systems Jetson TX2
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1

Hello,

We are having some issues controlling basic GPIO. We are looking to bitbang the SPI1 interface on the TX2 NX,

According to the pinmux sheet , the GPIO for SPI1 one is as follows.

gpiod (offset) sysfs
SPI1_SCK GPIO3_PV.01 169 489
SPI1_MISO GPIO3_PV.02 170 490
SPI1_MOSI GPIO3_PV.03 171 491
SPI1_CS0 GPIO3_PV.04 172 492

We can manipulate SPI_SCK fine, but we cannot control SPI1_MOSI or SPI_MISO. According to cat /sys/kernel/debug/gpio the GPIO we need are available (and not configured as SPI)

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However, when I try to use those pins I get device busy or in use. For example, trying to use SPI_1_MOSI, offset of 171 or 491.

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Similar behaviour occurs when using gpioset

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This makes me think something else is conflicting with the device.

I’m running L4T 32.5.1 and we have not modified the device tree.

Any ideas?

3

I just wanted to follow up with this.

It looks like the Jetson IO tool is not working as expected on the TX2 NX

L4T 32.5.1

By default Jetson IO shows the SPI1 pins are configured as SPI pins, however inspecting them with cat /sys/kernel/debug/gpio doesn’t show that they are configured as SPI, and the only spi available on the system is /dev/spidev3.0 and /dev/spidev3.1

Attempting to manually control the GPIO pins with sysfs does not work (resource unavailable or busy)

When you run the Jetson IO tool to configure the SPI pins as GPIO, the system reboots and Jetson IO indciates they are configured as GPIO, but you still cannot control the GPIO pins with sysfs.

L4T 32.6.1

By default Jetson IO shows the SPI1 pins are configured as GPIO pins, but attempting to manually control the GPIO pins with sysfs does not work (resource unavailable for busy)

When you run the Jetson IO tool to configure the pins as SPI, the system gets bricked. It shuts down and cannot boot again. When power is applied the nvidia logo is displayed on screen but the OS does not boot.

Any ideas @kayccc or @ShaneCCC ?

4

We will investigate this issue to have the suggestion soon.

7

GPIO Port V falls in AON domain.
#define TEGRA186_AON_GPIO_PORT_V 2

Actual value should be:
SPI1_MOSI GPIO3_PV.03 19 275
From sysfs, use value 275 for SPI1_MOSI and let us know if it works.

9

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