UFS layout

Hi NV:
I want to know whether the data and clock of UPHY have the requirements of “skew”?

No as you can see in the table PCIe Design Guidelines in DG.

So what is the function of UFS’s connected clock signal

Orin does not support UFS, please refer to the latest DG in DLC. https://developer.nvidia.com/embedded/secure/jetson/agx_orin/jetson_agx_orin_design_guide_dg-10653-001_v0.2.pdf

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