Xaiver power up sequence

hello,I has a question about Jetson Xaiver DG,in No MCU AND Auto-Power-On Case,when power on, what is the timing relationship between MODULE_POWER_ON and VDDIN_PWR_BAD_N? Can MODULE_POWER_ON becomes HIGH before VDDIN_PWR_BAD_N?

No, it should follow the sequence well. The timing is not so strict, but should be step by step.

Hello ,in No MCU AND Auto-Power-On Case,VDDIN_PWR_BAD_N is generated by TPS3808, about 6 ms after VDD_SRC(SYS_VIN_HV) is stable,VDDIN_PWR_BAD_N becomes HIGH. MODULE_POWER_ON is pulled up by VDD_5V(SYS_VIN_MV),when VDD_5V is stable, MODULE_POWER_ON becomes HIGH. So MODULE_POWER_ON becomes HIGH before VDDIN_PWR_BAD_N,How can xaiver work well?

TPS3808 is for VIN power loss not for power on sequence. The VIN_PWR_BAD is from RC design to VCC_SRC as you can see in P2822 schematic.

In addition, where do you get the “6ms” from?

In TPS3808 datasheet , after VDD_SRC(SYS_VIN_HV) is stable, RESET will remain
low (asserted) for the delay time . The delay time is determined by CT.IN P2822 ,CT is 1nF,and delay time is about 6 ms. So I think ODULE_POWER_ON becomes HIGH before VDDIN_PWR_BAD_N, and don’t match the power on squence. Can you explain it?Thanks.

No, module_power_on will be held low before vin_power_bad_n de-asserted, you can refer to P2822 schematic for more info.

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