Xavier as an endpoint


  1. Is there a document, that describes how to set the Xavier into pcie endpoint mode and back to RC?

  2. Where can we fined the host (x86) device driver for the Xavier when operating as an endpoint device?

  3. When the Xavier is configured as an EP, how many BARs does it presents to the host?

  4. When the Xavier is configured as an EP, which type of memory is behind the BARs? Kernel space of User space and how are these memory ranges are accessed form user mode code?

  5. As an EP, can the Xavier issue MWreq and MRdreq to host memory? Is there a built in DMA controller that enables transfer of data between the Xavier memory and the host Memory via the PCIe controller?


Please refer to the SDK documentation for this.